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11. 发明授权

US08722547B2 Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries 有权
标题翻译：用BC13基蚀刻化学法在高温下蚀刻具有高含氧层的高K电介质
公开(公告)号：US08722547B2
公开(公告)日：2014-05-13
申请号：US11736562
申请日：2007-04-17
申请人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
发明人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
IPC分类号： H01L21/31 , H01L21/311 , H01L29/51
CPC分类号： H01L21/31116 , H01L21/31122 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
摘要翻译：在电感耦合等离子体处理室中蚀刻具有高K电介质层和含氧化物或氮化物层的晶片，通过施加源电力来产生电感耦合等离子体，将包含BCl 3的气体引入室中，设定晶片的温度在100℃至350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中被蚀刻，将包括BCl 3的气体引入室中，将晶片的温度设定在20℃至并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCl 3的气体引入室中，晶片的温度在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。

12. 发明授权

US08133817B2 Shallow trench isolation etch process 失效
标题翻译：浅沟槽隔离蚀刻工艺
公开(公告)号：US08133817B2
公开(公告)日：2012-03-13
申请号：US12325220
申请日：2008-11-30
申请人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
发明人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L21/76224
摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
摘要翻译：本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

13. 发明授权

US07648914B2 Method for etching having a controlled distribution of process results 有权
标题翻译：具有受控分配处理结果的蚀刻方法
公开(公告)号：US07648914B2
公开(公告)日：2010-01-19
申请号：US11367004
申请日：2006-03-02
申请人： Thomas J. Kropewnicki , Theodoros Panagopoulos , Nicolas Gani , Wilfred Pau , Meihua Shen , John P. Holland
发明人： Thomas J. Kropewnicki , Theodoros Panagopoulos , Nicolas Gani , Wilfred Pau , Meihua Shen , John P. Holland
IPC分类号： H01L21/302
CPC分类号： H01L21/32137 , H01L22/20
摘要： Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.
摘要翻译：本发明的实施例通常提供蚀刻衬底的方法。在一个实施例中，该方法包括确定对应于衬底上的蚀刻副产物的均匀沉积速率的衬底温度目标分布，优选地调节衬底支撑件的第一部分相对于衬底支撑件的第二部分的温度以获得衬底上的衬底温度目标曲线，并且在优先调节的衬底支撑件上蚀刻衬底。在另一个实施例中，该方法包括在处理室中提供衬底，该处理室具有在处理室内的物质的可选择分布以及具有侧向温度控制的衬底支撑件，其中由衬底支撑件引导的温度曲线和物种分布的选择包括控制参数集，蚀刻第一层材料并使用不同的控制参数集分别蚀刻第二层材料。

14. 发明申请

US20070042603A1 Method for etching having a controlled distribution of process results 有权
标题翻译：具有受控分配处理结果的蚀刻方法
公开(公告)号：US20070042603A1
公开(公告)日：2007-02-22
申请号：US11367004
申请日：2006-03-02
申请人： Thomas Kropewnicki , Theodoros Panagopoulos , Nicolas Gani , Wilfred Pau , Meihua Shen , John Holland
发明人： Thomas Kropewnicki , Theodoros Panagopoulos , Nicolas Gani , Wilfred Pau , Meihua Shen , John Holland
IPC分类号： G01L21/30 , H01L21/302
CPC分类号： H01L21/32137 , H01L22/20
摘要： Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively using different control parameter sets.
摘要翻译：本发明的实施例通常提供蚀刻衬底的方法。在一个实施例中，该方法包括确定对应于衬底上的蚀刻副产物的均匀沉积速率的衬底温度目标分布，优选地调节衬底支撑件的第一部分相对于衬底支撑件的第二部分的温度以获得衬底上的衬底温度目标曲线，并且在优先调节的衬底支撑件上蚀刻衬底。在另一个实施例中，该方法包括在处理室中提供衬底，该处理室具有在处理室内的物质的可选择分布以及具有侧向温度控制的衬底支撑件，其中由衬底支撑件引导的温度曲线和物种分布的选择包括控制参数集，蚀刻第一层材料并使用不同的控制参数集分别蚀刻第二层材料。

15. 发明授权

US08101525B2 Method for fabricating a semiconductor device having a lanthanum-family-based oxide layer 失效
标题翻译：具有镧系氧化物层的半导体装置的制造方法
公开(公告)号：US08101525B2
公开(公告)日：2012-01-24
申请号：US12371085
申请日：2009-02-13
申请人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
发明人： Meihua Shen , Noel Sun , Nicolas Gani , Han-Hsiang Chen , Eric Pei , Weimin Zeng , Thorsten B. Lill , Uday Mitra , Ellie Y. Yieh
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31122 , H01L21/28123 , H01L21/28167 , H01L21/31105 , H01L21/31111 , H01L21/32139 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods for fabricating a semiconductor device having a lanthanum-family-based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.
摘要翻译：描述了制造具有镧族氧化物层的半导体器件的方法。具有镧族氧化物层的栅极叠层设置在基板的上方。镧族氧化物层的至少一部分被改性以形成镧族卤化物部分。用水蒸气处理除去镧族卤化物部分。

16. 发明授权

US07910488B2 Alternative method for advanced CMOS logic gate etch applications 失效
标题翻译：先进的CMOS逻辑门蚀刻应用的替代方法
公开(公告)号：US07910488B2
公开(公告)日：2011-03-22
申请号：US11777259
申请日：2007-07-12
申请人： Nicolas Gani , Meihua Shen , Shashank Deshmukh
发明人： Nicolas Gani , Meihua Shen , Shashank Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/31122 , H01L21/823828 , H01L29/517
摘要： Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.
摘要翻译：本文提供了用于制造CMOS逻辑门的蚀刻方法。在一些实施例中，蚀刻方法包括（a）提供具有第一堆叠和设置在其上的第二堆叠的衬底，第一堆叠包括高k电介质层，形成在高k电介质层上的金属层，以及形成在所述金属层上的第一多晶硅层，所述第二堆叠包括第二多晶硅层，其中所述第一和第二堆叠体的厚度基本相等; （b）同时蚀刻第一多晶硅层中的第一特征和第二多晶硅层中的第二特征，直到第一堆叠中的金属层暴露; （c）同时蚀刻金属层和第二多晶硅层以将相应的第一和第二特征延伸到第一和第二堆叠中; 和（d）蚀刻高k电介质层。

17. 发明申请

US20090170333A1 SHALLOW TRENCH ISOLATION ETCH PROCESS 失效
标题翻译： SHOWOW TRENCH隔离蚀刻工艺
公开(公告)号：US20090170333A1
公开(公告)日：2009-07-02
申请号：US12325220
申请日：2008-11-30
申请人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
发明人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L21/76224
摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
摘要翻译：本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

18. 发明申请

US20090017633A1 ALTERNATIVE METHOD FOR ADVANCED CMOS LOGIC GATE ETCH APPLICATIONS 失效
标题翻译：高级CMOS逻辑门控应用的替代方法
公开(公告)号：US20090017633A1
公开(公告)日：2009-01-15
申请号：US11777259
申请日：2007-07-12
申请人： NICOLAS GANI , Meihua Shen , Shashank Deshmukh
发明人： NICOLAS GANI , Meihua Shen , Shashank Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/31122 , H01L21/823828 , H01L29/517
摘要： Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.
摘要翻译：本文提供了用于制造CMOS逻辑门的蚀刻方法。在一些实施例中，蚀刻方法包括（a）提供具有第一堆叠和设置在其上的第二堆叠的衬底，第一堆叠包括高k电介质层，形成在高k电介质层上的金属层，以及形成在所述金属层上的第一多晶硅层，所述第二堆叠包括第二多晶硅层，其中所述第一和第二堆叠体的厚度基本相等; （b）同时蚀刻第一多晶硅层中的第一特征和第二多晶硅层中的第二特征，直到第一堆叠中的金属层暴露; （c）同时蚀刻金属层和第二多晶硅层以将相应的第一和第二特征延伸到第一和第二堆叠中; 和（d）蚀刻高k电介质层。

19. 发明授权

US10658161B2 Method and apparatus for reducing particle defects in plasma etch chambers 有权
公开(公告)号：US10658161B2
公开(公告)日：2020-05-19
申请号：US13174090
申请日：2011-06-30
申请人： Xikun Wang , Andrew Nguyen , Changhun Lee , Xiaoming He , Meihua Shen
发明人： Xikun Wang , Andrew Nguyen , Changhun Lee , Xiaoming He , Meihua Shen
IPC分类号： H01L21/3213 , H01J37/32
摘要： In-situ low pressure chamber cleans and gas nozzle apparatus for plasma processing systems employing in-situ deposited chamber coatings. Certain chamber clean embodiments for conductor etch applications include an NF3-based plasma clean performed at pressures below 30 mT to remove in-situ deposited SiOx coatings from interior surfaces of a gas nozzle hole. Embodiments include a gas nozzle with bottom holes dimensioned sufficiently small to reduce or prevent the in-situ deposited chamber coatings from building up a SiOx deposits on interior surfaces of a nozzle hole.

20. 发明申请

US20100018648A1 WORKPIECE SUPPORT FOR A PLASMA REACTOR WITH CONTROLLED APPORTIONMENT OF RF POWER TO A PROCESS KIT RING 审中-公开
标题翻译：用于等离子体反应器的工作支持，具有控制的RF功率分配到工艺套件环
公开(公告)号：US20100018648A1
公开(公告)日：2010-01-28
申请号：US12178032
申请日：2008-07-23
申请人： KENNETH S. COLLINS , Douglas A. Buchberger, JR. , Kartik Ramaswamy , Shahid Rauf , Hiroji Hanawa , Jennifer Y. Sun , Andrew Nguyen , Thorsten B. Lill , Meihua Shen
发明人： KENNETH S. COLLINS , Douglas A. Buchberger, JR. , Kartik Ramaswamy , Shahid Rauf , Hiroji Hanawa , Jennifer Y. Sun , Andrew Nguyen , Thorsten B. Lill , Meihua Shen
IPC分类号： H01L21/3065
CPC分类号： H01J37/32642 , H01J37/32082 , H01J37/32174 , H01J37/32623 , H01J2237/2001 , H01L21/6833
摘要： In an electrostatic chuck, RF bias power is separately applied to a workpiece and to a process kit collar surrounding the workpiece. At least one variable impedance element governed by a system controller adjusts the apportionment of RF bias power between the workpiece and the process kit collar, allowing dynamic adjustment of the plasma sheath electric field at the extreme edge of the workpiece, for optimum electric field uniformity under varying plasma conditions, for example.
摘要翻译：在静电卡盘中，RF偏置功率分别施加到工件和围绕工件的处理套件套环。由系统控制器控制的至少一个可变阻抗元件调节工件和工艺套件套环之间的RF偏置功率的分配，允许动态调整工件最末端处的等离子体护套电场，以获得最佳的电场均匀度改变等离子体条件。

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