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11. 发明授权

US06492715B1 Integrated semiconductor package 有权
标题翻译：集成半导体封装
公开(公告)号：US06492715B1
公开(公告)日：2002-12-10
申请号：US09660866
申请日：2000-09-13
申请人： Voya R. Markovich , Douglas O. Powell , Amit K. Sarkhel
发明人： Voya R. Markovich , Douglas O. Powell , Amit K. Sarkhel
IPC分类号： H01L2302
CPC分类号： H01L21/563 , H01L23/055 , H01L23/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , H01L2924/00 , H01L2224/0401
摘要： The present invention provides an integrated semiconductor module comprising a chip, interposer, and substrate. The module is adapted to be mounted on a traditional circuit card carrying multiple other components. The chip of the present invention can be a conventional IC chip or chip package, including ball grid array packages, and will simply be referred to hereinafter as a “chip.” The interposer of the present invention is a conventional thin film interposer, such as those composed of a polyimide material and fabricated on a glass carrier plate. The substrate of the present invention is a conventional circuitized substrate, such as a BGA or laminate substrate, that is commonly employed in carrying a chip on a circuit card. In its assembled state, the present invention comprises an interposer mounted on top of a substrate with the electrical contacts formed on the lower surface of the interposer positioned in electrical communication with respective ones of electrical contacts formed on the upper surface of the substrate. A non-conductive material, such as an epoxy resin, fills the voids between the interposer and substrate created by the electrical connections. The epoxy resin forms a mechanical bond between the interposer and substrate, thereby enhancing the structural integrity of the unit. Moreover, by filling the voids between the electrical connections, essentially no foreign particles can become entrapped therein and cause electrical malfunctions. Accordingly, the environmental and operational integrity of the unit is also enhanced.
摘要翻译：本发明提供了一种包括芯片，插入器和衬底的集成半导体模块。该模块适于安装在承载多个其他部件的传统电路卡上。本发明的芯片可以是包括球栅阵列封装在内的常规IC芯片或芯片封装，并且在下文中简单地称为“芯片”。本发明的插入件是常规的薄膜插入件，例如由聚酰亚胺材料构成的薄膜插入件，并且制造在玻璃载体板上。本发明的基板是通常用于承载电路卡上的芯片的常规电路化基板，例如BGA或层叠基板。在其组装状态下，本发明包括安装在基板的顶部上的插入件，其中形成在插入件的下表面上的电触点定位成与形成在基板的上表面上的相应电触头电连通。诸如环氧树脂的非导电材料填充由电连接产生的插入件和衬底之间的空隙。环氧树脂在插入物和基材之间形成机械结合，从而提高了单元的结构完整性。此外，通过填充电连接之间的空隙，基本上不会在其中夹带杂质颗粒并引起电气故障。因此，该单位的环境和运营完整性也得到提高。

12. 发明授权

US5557844A Method of preparing a printed circuit board 失效
标题翻译：印刷电路板的制备方法
公开(公告)号：US5557844A
公开(公告)日：1996-09-24
申请号：US463344
申请日：1995-06-05
申请人： Anilkumar C. Bhatt , Roy H. Magnuson , Voya R. Markovich , Konstantinos I. Papathomas , Douglas O. Powell
发明人： Anilkumar C. Bhatt , Roy H. Magnuson , Voya R. Markovich , Konstantinos I. Papathomas , Douglas O. Powell
IPC分类号： H01L23/538 , H05K1/11 , H05K3/00 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/0094 , H01L23/5384 , H05K1/112 , H05K3/4602 , H01L2224/16 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K2201/092 , H05K2201/09472 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09845 , H05K2201/10734 , H05K2203/0191 , H05K2203/0278 , H05K3/0023 , H05K3/429 , Y10T29/49126 , Y10T29/49165
摘要： Disclosed is a printed circuit board and a method of preparing the printed circuit board, The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.
摘要翻译：公开了印刷电路板和制备印刷电路板的方法。印刷电路板具有两种类型的电镀通孔。第一类型的电镀通孔延伸到印刷电路板的外表面并通过印刷电路板的外表面，用于接收针式通孔模块或部件销。第二种类型的电镀通孔用于表面贴装技术，并终止在印刷电路板的外表面之下。这些电镀通孔包含填充组合物。

13. 发明授权

US5487218A Method for making printed circuit boards with selectivity filled plated through holes 失效
标题翻译：制造具有选择性填充电镀通孔的印刷电路板的方法
公开(公告)号：US5487218A
公开(公告)日：1996-01-30
申请号：US342533
申请日：1994-11-21
申请人： Anilkumar C. Bhatt , Roy H. Magnuson , Voya R. Markovich , Konstantinos I. Papathomas , Douglas O. Powell
发明人： Anilkumar C. Bhatt , Roy H. Magnuson , Voya R. Markovich , Konstantinos I. Papathomas , Douglas O. Powell
IPC分类号： H01L23/538 , H05K1/11 , H05K3/00 , H05K3/42 , H05K3/46 , H01K3/10
CPC分类号： H05K3/0094 , H01L23/5384 , H05K1/112 , H05K3/4602 , H01L2224/16 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K2201/092 , H05K2201/09472 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09845 , H05K2201/10734 , H05K2203/0191 , H05K2203/0278 , H05K3/0023 , H05K3/429 , Y10T29/49126 , Y10T29/49165
摘要： Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.
摘要翻译：公开了印刷电路板和制备印刷电路板的方法。印刷电路板有两种电镀通孔。第一类型的电镀通孔延伸到印刷电路板的外表面并通过印刷电路板的外表面，用于接收针式通孔模块或部件销。第二种类型的电镀通孔用于表面贴装技术，并终止在印刷电路板的外表面之下。这些电镀通孔包含填充组合物。

14. 发明授权

US5137461A Separable electrical connection technology 失效
标题翻译：可分离的电气连接技术
公开(公告)号：US5137461A
公开(公告)日：1992-08-11
申请号：US606007
申请日：1990-10-30
申请人： Perminder S. Bindra , Jerome J. Cuomo , Thomas P. Gall , Anthony P. Ingraham , Sung K. Kang , Jungihl Kim , Paul Lauro , David N. Light , Voya R. Markovich , Ekkehard F. Miersch , Jaynal A. Molla , Douglas O. Powell , John J. Ritsko , George J. Saxenmeyer, Jr. , Jack A. Varcoe , George F. Walker
发明人： Perminder S. Bindra , Jerome J. Cuomo , Thomas P. Gall , Anthony P. Ingraham , Sung K. Kang , Jungihl Kim , Paul Lauro , David N. Light , Voya R. Markovich , Ekkehard F. Miersch , Jaynal A. Molla , Douglas O. Powell , John J. Ritsko , George J. Saxenmeyer, Jr. , Jack A. Varcoe , George F. Walker
IPC分类号： H01R4/26 , H01R4/58 , H01R13/22 , H05K3/32
CPC分类号： H01R4/26 , H01L24/83 , H01L24/90 , H01L24/98 , H01R13/22 , H01R4/58 , H05K3/325 , H01L2224/13111 , H01L2224/29111 , H01L2224/2919 , H01L2224/48227 , H01L2224/8319 , H01L2224/838 , H01L2224/85444 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , Y10T29/49224
摘要： A separable and reconnectable connection for electrical equipment is provided that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated in control of damage in lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact, by strengthening through coating and base reinforcement and a deformable coating. The contacts are fabricated by physical and chemical processes including sputtering, normal and pulse electroplating and chemical vapor deposition. The contacts on completion are provided with a surrounding immobilizing material that enhances rigidity.
摘要翻译：提供一种用于电气设备的可分离和可重新连接的连接件，其适于小型化，其中容纳从平面部分一体地附接和突出的垂直交叉构件，以控制与相对的类似接触件配合时发生的横向位移损坏。通过提供一个或多个共形相对的接触，通过加强涂层和基底加强件以及可变形的涂层来容纳横向应力来避免位移损伤。接触是通过物理和化学过程制造的，包括溅射，正常和脉冲电镀以及化学气相沉积。完成的触点设置有增强刚性的周边固定材料。

15. 发明申请

US20080217050A1 MULTI-LAYERED INTERCONNECT STRUCTURE USING LIQUID CRYSTALLINE POLYMER DIELECTRIC 有权
标题翻译：使用液晶聚合物电介质的多层互连结构
公开(公告)号：US20080217050A1
公开(公告)日：2008-09-11
申请号：US11873435
申请日：2007-10-17
申请人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
发明人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
IPC分类号： H01R12/04 , B29C65/48
CPC分类号： H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/462 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4641 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1092
摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.
摘要翻译：多层互连结构和形成方法。在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

16. 发明授权

US07301108B2 Multi-layered interconnect structure using liquid crystalline polymer dielectric 有权
标题翻译：使用液晶聚合物电介质的多层互连结构
公开(公告)号：US07301108B2
公开(公告)日：2007-11-27
申请号：US10959711
申请日：2004-10-05
申请人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
发明人： Frank D. Egitto , Donald S. Farquhar , Voya R. Markovich , Mark D. Poliks , Douglas O. Powell
IPC分类号： H05K1/11 , H01R12/04
CPC分类号： H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/462 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4641 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T156/1092
摘要： A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.
摘要翻译：多层互连结构和形成方法。在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。

17. 发明授权

US5597469A Process for selective application of solder to circuit packages 失效
标题翻译：焊料选择性地应用于电路封装的工艺
公开(公告)号：US5597469A
公开(公告)日：1997-01-28
申请号：US387686
申请日：1995-02-13
申请人： Charles F. Carey , Kenneth M. Fallon , Voya R. Markovich , Douglas O. Powell , Gary P. Vlasak , Richard S. Zarr
发明人： Charles F. Carey , Kenneth M. Fallon , Voya R. Markovich , Douglas O. Powell , Gary P. Vlasak , Richard S. Zarr
IPC分类号： C25D5/02 , C25D5/08 , H01L21/48 , H01L21/60 , H05K3/24 , H05K3/34
CPC分类号： H01L24/81 , C25D5/022 , C25D5/08 , H01L21/4825 , H01L21/4853 , H05K3/241 , H05K3/3473 , H01L2224/11849 , H01L2224/119 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H05K2203/043 , H05K2203/054
摘要： Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.
摘要翻译：可以通过在具有孔或凹槽（例如盲孔）的电介质层的表面上沉积导电材料层并且暴露于其中的导体和/或焊盘而形成具有高体积精度和形状均匀性的小的，紧密间隔的焊料材料沉积物孔或凹槽，导电材料的掩模区域和另外的图案化介电层，将电镀焊料材料电镀到由掩模曝光的导电材料的区域上，通过选择性蚀刻和至少从至少有孔电介质层的一部分表面。盲孔内电镀的均匀性通过流体喷射和阴极搅拌的组合增强。在电镀之前，可以通过在浸没池中用焊料材料的构成成分代替导体材料来避免所得到的焊料沉积物中的过多的导体材料。

18. 发明授权

US06423905B1 Printed wiring board with improved plated through hole fatigue life 有权
标题翻译：印刷电路板，具有改善的电镀通孔疲劳寿命
公开(公告)号：US06423905B1
公开(公告)日：2002-07-23
申请号：US09562109
申请日：2000-05-01
申请人： William L. Brodsky , Kevin T. Knadle , John M. Lauffer , Douglas O. Powell , David J. Russell
发明人： William L. Brodsky , Kevin T. Knadle , John M. Lauffer , Douglas O. Powell , David J. Russell
IPC分类号： H05K103
CPC分类号： H05K3/4688 , H05K1/0271 , H05K3/429 , H05K2201/0133 , H05K2201/0195
摘要： A printed wiring board having a layered composite of metal planes and dielectric layers. At least one of the dielectric layers has a modulus lower than the modulus of the remaining dielectric material layers. A plating, extending through the layered composite, has a first land on a first external surface of the layered composite, a second land on a second external surface of the layered composite, and a barrel extending between the first land and the second land. The lower modulus dielectric material layer deforms during thermal excursions of the printed wiring board in such a way as to reduce the strains imposed on both the lands and the barrel of the plated through holes.
摘要翻译：一种具有金属平面和电介质层的复合层的印刷电路板。电介质层中的至少一个具有低于剩余介电材料层的模量的模量。延伸穿过层状复合材料的电镀具有在层状复合材料的第一外表面上的第一焊盘，层状复合材料的第二外表面上的第二焊盘，以及在第一焊盘和第二焊盘之间延伸的镜筒。在印刷线路板的热偏移期间，较低模量的介电材料层变形，以便减小施加在电镀通孔的焊盘和圆筒上的应变。

19. 发明授权

US09099458B2 Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权
标题翻译：在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法
公开(公告)号：US09099458B2
公开(公告)日：2015-08-04
申请号：US13539480
申请日：2012-07-01
申请人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
发明人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC分类号： H05K1/11 , H05K1/09 , H01L23/498 , H05K3/46 , H05K1/02
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.
摘要翻译：用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。盘状结构包括支撑多个堆叠的通孔的平板通孔平台。镀层通孔着色包括蚀刻图案。

20. 发明授权

US08866026B2 Construction of reliable stacked via in electronic substrates—vertical stiffness control method 有权
标题翻译：在电子基板中构建可靠的堆叠通孔 - 垂直刚度控制方法
公开(公告)号：US08866026B2
公开(公告)日：2014-10-21
申请号：US13569826
申请日：2012-08-08
申请人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
发明人： Karan Kacker , Douglas O. Powell , David L. Questad , David J. Russell , Sri M. Sri-Jayantha
IPC分类号： H05K1/11 , H05K1/09 , H05K3/46 , H01L23/498 , H05K1/02
CPC分类号： H01L23/49827 , H01L23/49838 , H01L2224/05001 , H01L2224/05548 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/15311 , H05K1/0271 , H05K1/116 , H05K3/4602 , H05K2201/0347 , H05K2201/09454 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/0969 , Y10T29/49155 , H01L2224/05599 , H01L2224/05099
摘要： A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.
摘要翻译：用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。盘状结构包括厚度基本为3μm的板状通孔着落。镀层通孔着色包括蚀刻图案和铜顶表面。

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