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11. 发明授权

US06566244B1 Process for improving mechanical strength of layers of low k dielectric material 有权
标题翻译：用于提高低k介电材料层的机械强度的方法
公开(公告)号：US06566244B1
公开(公告)日：2003-05-20
申请号：US10138609
申请日：2002-05-03
申请人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
发明人： Charles E. May , Venkatesh P. Gopinath , Peter J. Wright
IPC分类号： H01L214763
CPC分类号： H01L23/562 , H01L21/76801 , H01L21/76829 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.
摘要翻译：一种用于选择性地增强低k介电材料的部分的方法，其包括首先形成低k电介质层，然后在需要加强的低k层的部分中在低k层中形成开口，然后用增强材料填充开口，优选地具有比低k介电材料更高的杨氏弹性模量的增强材料。低k电介质材料的某些部分的这种选择性增强可以包括用增强材料选择性地增强接合焊盘下面的低k电介质材料。低k电介质材料可以通过在低k电介质层的下部形成的低k电介质材料中的开口加强，其中覆盖层将形成在低k电介质材料上。覆盖层的随后的形成将同时用封盖材料填充开口，该封盖材料然后也可以用作开口中的增强材料。

12. 发明授权

US06362510B1 Semiconductor topography having improved active device isolation and reduced dopant migration 有权
标题翻译：半导体形貌具有改进的有源器件隔离和减少掺杂剂迁移
公开(公告)号：US06362510B1
公开(公告)日：2002-03-26
申请号：US09206550
申请日：1998-12-07
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L21/28202 , H01L21/02381 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/2822 , H01L21/762 , H01L29/1083 , H01L29/36 , H01L29/518 , H01L29/6659 , H01L29/66651
摘要： A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.
摘要翻译：提出一种用于制造集成电路的方法，其中提供了在其上表面上形成有电介质层的半导体衬底。在从半导体衬底的上表面延伸到电介质层的上表面的电介质层中形成凹槽。然后在沟槽内生长硅外延层。阻挡原子与外延生长工艺同时并入硅外延层。

13. 发明授权

US06348413B1 High pressure N2 RTA process for TiS2 formation 有权
标题翻译：用于TiS2形成的高压N2 RTA工艺
公开(公告)号：US06348413B1
公开(公告)日：2002-02-19
申请号：US09157855
申请日：1998-09-21
申请人： Timothy Z. Hossain , Charles E. May
发明人： Timothy Z. Hossain , Charles E. May
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/324
摘要： In one aspect of the present invention, a method of forming a layer of silicide on a surface of a silicon-containing structure surface that is separated from a first structure by a second structure is provided. The method includes the steps of forming a layer of silicide-forming material on the surface of the silicon-containing structure, and the first and second structures. The layer of silicide-forming material is annealed in an ambient containing a nitrogen bearing species at a pressure greater than about one atmosphere to form the layer of silicide on the surface of the silicon-containing structure. The nitrogen bearing species reacts with the silicide-forming material to retard the formation of silicide on the third structure. The method reduces the potential for silicide bridging between, for example, the gate and source/drain regions of a transistor during silicide contact formation.
摘要翻译：在本发明的一个方面中，提供了在通过第二结构与第一结构分离的含硅结构表面的表面上形成硅化物层的方法。该方法包括以下步骤：在含硅结构的表面上形成硅化物形成层，以及第一和第二结构。硅化物形成材料层在含有含氮物质的环境中在大于约一个大气压的温度下退火，以在含硅结构的表面上形成硅化物层。含氮物质与硅化物形成材料反应以阻止第三结构上的硅化物的形成。该方法在硅化物接触形成期间降低例如晶体管的栅极和源极/漏极区域之间的硅化物桥接的可能性。

14. 发明授权

US06222230B1 Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation 有权
标题翻译：用增强的梯度侧壁制造升高的源极/漏极的方法，用于与间隔物形成集成的晶体管缩放
公开(公告)号：US06222230B1
公开(公告)日：2001-04-24
申请号：US09204967
申请日：1998-12-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2976
CPC分类号： H01L29/66621 , H01L21/823418 , H01L21/823468 , H01L21/823487 , H01L29/4232 , H01L29/4238
摘要： An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.
摘要翻译：提供集成电路及其制造晶体管的方法。在一个方面，集成电路包括基板和位于基板的多个有源区上的多个晶体管。每个晶体管具有位于衬底中的掺杂区域，位于衬底中的锥形沟槽中的绝缘层，其延伸穿过并将掺杂区域划分为第一源极/漏极区域和第二源极/漏极区域。绝缘层是具有基部的沟道形状，第一向上倾斜的侧壁和第二向上倾斜的侧壁。栅电极位于绝缘层上。通道形栅极电介质层需要较少的水平衬底面积，使给定衬底具有更高的堆积密度。倾斜的侧壁作为间隔件加倍，使工艺简化。

15. 发明授权

US06207544B1 Method of fabricating ultra thin nitride spacers and device incorporating same 有权
标题翻译：制造超薄氮化物间隔物的方法和结合其的装置
公开(公告)号：US06207544B1
公开(公告)日：2001-03-27
申请号：US09207808
申请日：1998-12-09
申请人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
发明人： Thien T. Nguyen , Mark I. Gardner , Charles E. May
IPC分类号： H01L213065
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L29/6656
摘要： The present invention is directed to a method of fabricating very thin silicon nitride spacers on a transistor, and to a device comprising such spacers. In one illustrative embodiment, the method comprises forming a gate dielectric above a surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and forming a layer of silicon nitride above the substrate. The method further comprises performing at least one anisotropic etching process on the layer of silicon nitride using an etching recipe comprised of helium (He), sulfur hexafluoride (SF6) and hydrogen bromide (HBr). The transistor of the present invention is comprised of a gate dielectric positioned above the surface of a semiconducting substrate and a gate conductor positioned above the gate dielectric. The transistor further comprises a plurality of source/drain regions formed in the substrate adjacent the gate dielectric and a plurality of sidewall spacers comprised of silicon nitride, each of the sidewall spacers having a thickness that ranges from approximately 200-350 Å.
摘要翻译：本发明涉及一种在晶体管上制造非常薄的氮化硅间隔物的方法以及包括这种间隔物的装置。在一个说明性实施例中，该方法包括在半导体衬底的表面上形成栅极电介质，在栅极电介质上形成栅极导体，并在衬底上方形成氮化硅层。该方法还包括使用由氦（He），六氟化硫（SF 6）和溴化氢（HBr）组成的蚀刻配方对氮化硅层进行至少一个各向异性蚀刻工艺。本发明的晶体管包括位于半导体衬底的表面上方的栅极电介质和位于栅极电介质上方的栅极导体。晶体管还包括形成在邻近栅极电介质的衬底中的多个源极/漏极区域和由氮化硅构成的多个侧壁间隔物，每个侧壁间隔物的厚度范围为约200-350埃。

16. 发明授权

US06188106B1 MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties 有权
标题翻译： MOSFET具有高度掺杂的沟道衬垫和掺杂剂密封，以提供增强的器件特性
公开(公告)号：US06188106B1
公开(公告)日：2001-02-13
申请号：US09146410
申请日：1998-09-03
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L2978
CPC分类号： H01L29/51 , H01L21/26533 , H01L29/0649 , H01L29/1079 , H01L29/665 , H01L29/6659
摘要： A fabrication process and integrated circuit are provided in which a transistor having increased resistance to punchthrough and decreased channel capacitance is formed. A liner layer is formed within the active region of a transistor to minimize punchthrough. A barrier layer is then formed between the liner layer and the upper surface of the semiconductor substrate. The barrier layer preferably inhibits migration of the liner ions into the junction and channel regions of the transistors during subsequent processing steps. Such migration could deleteriously affect transistor function by, e.g., increasing the threshold voltage and thus decreasing the drive current. The barrier layer also preferably facilitates formation of shallow junctions. In an embodiment, the liner layer may include p-type ions such as boron and the barrier layer may include nitrogen implanted into the semiconductor substrate. Alternatively, the barrier layer may include nitrogen-incorporated epitaxially grown silicon.
摘要翻译：提供一种制造工艺和集成电路，其中形成具有增加的穿透电阻和降低的沟道电容的晶体管。在晶体管的有源区内形成衬垫层以最小化穿透。然后在衬垫层和半导体衬底的上表面之间形成阻挡层。阻挡层优选地在随后的处理步骤期间抑制衬里离子迁移到晶体管的结和沟道区中。这种迁移可以通过例如增加阈值电压并从而降低驱动电流来有害地影响晶体管功能。阻挡层还优选有利于形成浅结。在一个实施例中，衬垫层可以包括诸如硼的p型离子，并且阻挡层可以包括注入到半导体衬底中的氮。或者，阻挡层可以包括掺入氮的外延生长的硅。

17. 发明授权

US6159804A Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length 失效
标题翻译：制造具有超短沟道长度的晶体管的一次性侧壁氧化制造方法
公开(公告)号：US6159804A
公开(公告)日：2000-12-12
申请号：US145663
申请日：1998-09-02
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/72
CPC分类号： H01L29/66659 , H01L21/28132 , H01L21/823425 , H01L21/823468
摘要： The present invention is directed to a method of making a transistor having a very short channel length. The method generally comprises forming a plurality of process layers above a surface of a semiconducting substrate, one of the process layers being comprised of a gate dielectric material and another of the process layers being comprised of a gate conductor material. The method further comprises patterning the plurality of process layers to define an opening and forming a first sidewall spacer in the opening adjacent at least the process layer comprised of a gate conductor material. The method continues with the formation of a gate conductor mask by oxidation of a portion of at least one of the process layers other than those layers comprised of a gate dielectric material and the gate conductor material. A portion of the process layer comprised of a gate conductor material is then removed to define a gate conductor positioned beneath the gate conductor mask, followed by the formation of a second sidewall spacer adjacent the gate conductor. Thereafter, at least one source/drain region is formed to complete the transistor formation. The present invention further comprises a transistor having a channel length of less than 1000 .ANG..
摘要翻译：本发明涉及一种制造具有非常短的通道长度的晶体管的方法。该方法通常包括在半导体衬底的表面上方形成多个工艺层，其中一个工艺层由栅极电介质材料构成，另一个工艺层由栅极导体材料构成。该方法还包括对多个处理层进行图案化以限定开口，并且在开口中形成邻近至少由栅极导体材料构成的工艺层的第一侧壁间隔物。该方法继续通过除了由栅极电介质材料和栅极导体材料构成的那些层之外的至少一个工艺层的一部分的氧化形成栅极导体掩模。然后移除由栅极导体材料构成的工艺层的一部分，以限定位于栅极导体掩模下方的栅极导体，随后形成邻近栅极导体的第二侧壁间隔物。此后，形成至少一个源极/漏极区以完成晶体管的形成。本发明还包括具有小于1000安培的通道长度的晶体管。

18. 发明授权

US6127235A Method for making asymmetrical gate oxide thickness in channel MOSFET region 失效
标题翻译：在沟道MOSFET区域中制造不对称栅极氧化物厚度的方法
公开(公告)号：US6127235A
公开(公告)日：2000-10-03
申请号：US2656
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51
CPC分类号： H01L21/28176 , H01L21/28185 , H01L29/42368 , H01L29/518 , H01L29/66659 , H01L21/28114 , H01L21/28202 , H01L21/28211 , H01L29/42376
摘要： A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of a single spacer located within the gate at the sidewall nearest the drain of the semiconductor device. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacer and the other sidewall of the gate. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.
摘要翻译：半导体器件具有栅极，第一材料具有邻近半导体衬底的第一介电常数和邻近半导体衬底的具有第二介电常数的第二材料。然后将诸如多晶硅的导体放置在栅极上，使得第一和第二材料夹在导体和半导体衬底之间。由于两种材料的介电常数不同，栅极的作用就像具有至少两个厚度的单个电介质的栅极。一个介电常数大于另一介电常数。较高的介电常数材料由最靠近半导体器件的漏极的侧壁处的栅极内的单个间隔件组成。二氧化硅层位于半导体衬底上的间隔件和栅极的另一个侧壁之间。可以调整间隔件的厚度以优化半导体器件的性能。

19. 发明授权

US6090694A Local interconnect patterning and contact formation 失效
标题翻译：局部互连图案和接触形成
公开(公告)号：US6090694A
公开(公告)日：2000-07-18
申请号：US991742
申请日：1997-12-16
申请人： Fred N. Hause , Charles E. May , Mark I. Gardner
发明人： Fred N. Hause , Charles E. May , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76832 , Y10S438/952
摘要： A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.
摘要翻译：用于形成半导体器件以产生用于在器件内互连电平或形成器件中的外表面和内部层之间的连接的无失真通孔的方法包括以下步骤：将与蚀刻停止相邻的材料 ARC的层。换句话说，蚀刻停止放置在形成在器件内的层上的金属层上。之后是二氧化硅层（SiO 2），然后是与蚀刻停止层相似的材料层。光刻胶放置在与蚀刻停止相似的材料层上。光致抗蚀剂暴露于光以形成通孔的位置。类似于蚀刻停止的材料层，然后在单独的蚀刻步骤中去除SiO 2层，以形成从抗蚀剂到蚀刻停止件的通孔路径，该蚀刻停止件邻近选定为由通孔相互连接的层的金属。然后可以除去抗蚀剂。这使得材料类似于位于SiO 2层的一个表面附近的蚀刻停止层，并且使蚀刻停止件覆盖通孔孔中的金属。现在可以使用一个蚀刻步骤去除覆盖通孔开口中的金属的蚀刻停止层，并且去除类似于位于SiO 2上的蚀刻停止层的材料。

20. 发明授权

US6067154A Method and apparatus for the molecular identification of defects in semiconductor manufacturing using a radiation scattering technique such as raman spectroscopy 失效
标题翻译：使用诸如拉曼光谱法的辐射散射技术来分子鉴定半导体制造中的缺陷的方法和装置
公开(公告)号：US6067154A
公开(公告)日：2000-05-23
申请号：US177930
申请日：1998-10-23
申请人： Tim Z. Hossain , Charles E. May
发明人： Tim Z. Hossain , Charles E. May
IPC分类号： G01N21/65 , G01N21/00
CPC分类号： G01N21/65 , G01N2021/656
摘要： A method and apparatus are provided for obtaining molecular information about materials at a selected site on or in a semiconductor topography. In a preferred embodiment, the selected site is a defect from a defect map generated by an automated wafer inspection system. A sample stage and drive/alignment system are used to move the semiconductor topography such that a selected defect is aligned with the illumination provided by a radiation scattering measurement system. A Raman spectroscopy system may be used for the radiation scattering measurement. The intensity and frequency of inelastically scattered radiation from the vicinity of the selected defect is compared to standard spectra to determine the chemical composition and material phase of the region analyzed. The depth into the topography probed may be adjusted by changing the wavelength of radiation used in the Raman spectroscopy measurement. In this way, the source of a particular defect, even if buried in the topography during the semiconductor fabrication process, may be determined. Knowledge of the fabrication process guides selection of the appropriate depths to be analyzed.
摘要翻译：提供了一种方法和装置，用于获得关于在半导体形貌上或半导体形貌中的选定部位的材料的分子信息。在优选实施例中，所选择的位置是由自动晶片检查系统生成的缺陷图的缺陷。使用样品台和驱动/对准系统来移动半导体形貌，使得所选择的缺陷与由辐射散射测量系统提供的照明对准。拉曼光谱系统可用于辐射散射测量。将来自所选缺陷附近的非弹性散射辐射的强度和频率与标准光谱进行比较，以确定所分析区域的化学成分和材料相。可以通过改变拉曼光谱测量中使用的辐射波长来调整探测的地形深度。以这种方式，即使在半导体制造过程中掩埋在地形中，也可以确定特定缺陷的源。制造过程的知识指导了要分析的适当深度的选择。

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