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11. 发明申请

US20100188886A1 Implementing Enhanced SRAM Stability and Enhanced Chip Yield With Configurable Wordline Voltage Levels 有权
标题翻译：通过可配置的字线电压电平实现增强的SRAM稳定性和增强的芯片产量
公开(公告)号：US20100188886A1
公开(公告)日：2010-07-29
申请号：US12360242
申请日：2009-01-27
申请人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
发明人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
IPC分类号： G11C11/00 , G11C29/00
CPC分类号： G11C8/08 , G11C11/41 , G11C11/413 , G11C11/419 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
摘要翻译：一种内置自检（ABIST）方法的阵列和用于使用可配置字线电压电平实现增强型静态随机存取存储器（SRAM）稳定性和增强的芯片产量的电路，以及提供主题电路所在的设计结构。字线连接到SRAM存储单元。多个字线电压下拉器件连接到字线。相应的字线电压控制输入信号被施加到多个字线电压下拉器件中的每一个以选择性地调节字线的电压电平。

12. 发明申请

US20090116298A1 APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写入性能评估的设备
公开(公告)号：US20090116298A1
公开(公告)日：2009-05-07
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

13. 发明授权

US07911827B2 Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels 有权
标题翻译：通过可配置的字线电压电平实现增强的SRAM稳定性和增强的芯片产量
公开(公告)号：US07911827B2
公开(公告)日：2011-03-22
申请号：US12360242
申请日：2009-01-27
申请人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
发明人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/41 , G11C11/413 , G11C11/419 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/5002
摘要： An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
摘要翻译：一种内置自检（ABIST）方法的阵列和用于使用可配置字线电压电平实现增强型静态随机存取存储器（SRAM）稳定性和增强的芯片产量的电路，以及提供主题电路所在的设计结构。字线连接到SRAM存储单元。多个字线电压下拉器件连接到字线。相应的字线电压控制输入信号被施加到多个字线电压下拉器件中的每一个以选择性地调节字线的电压电平。

14. 发明授权

US07788554B2 Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation 失效
标题翻译：体现在用于实现SRAM单元写入性能评估的机器可读介质中的设计结构
公开(公告)号：US07788554B2
公开(公告)日：2010-08-31
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：提供了体现在用于实现静态随机存取存储器（SRAM）单元写入性能评估的机器可读介质中的设计结构。 SRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

15. 发明授权

US07724585B2 Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability 失效
标题翻译：实现本地评估多米诺骨牌SRAM，增强SRAM单元的稳定性
公开(公告)号：US07724585B2
公开(公告)日：2010-05-25
申请号：US12195117
申请日：2008-08-20
申请人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
发明人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
IPC分类号： G11C7/06 , G06F17/50
CPC分类号： G11C11/413
摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
摘要翻译：一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。能够对相关联的SRAM单元组进行读和写操作的SRAM本地评估电路包括真实和补码位线，单个写入数据传播输入，预充电信号和预充电写入信号。传递门装置连接在补码位线和写入数据传播输入之间。晶体管堆叠与真正位线和地之间的预充电装置串联连接。在读取操作期间，预充电写入信号禁止连接在补码位线和写入数据传播输入之间的通道器件。在写操作期间，预充电写入信号使得连接在补码位线和写入数据传播输入之间的通道器件能够激活晶体管堆叠。

16. 发明授权

US07737757B2 Low power level shifting latch circuits with gated feedback for high speed integrated circuits 失效
标题翻译：低功率电平移位锁存电路，具有门控反馈用于高速集成电路
公开(公告)号：US07737757B2
公开(公告)日：2010-06-15
申请号：US12178071
申请日：2008-07-23
申请人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
发明人： Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson , Jesse Daniel Smith
IPC分类号： H03K19/0175
CPC分类号： H03K3/356121
摘要： Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
摘要翻译：具有用于高速集成电路的门控反馈的低功率电平移位器锁存电路，以及设有主题电路所在的设计结构。操作在第一电压源的域中的锁存器输入级接收响应于通过预定时钟信号使能的数据输入。耦合到锁存器输入级的锁存器存储元件包括在第二电压源的区域中操作的锁存器输出级提供具有与第二电压源相对应的电压电平的数据输出。闩锁存储元件包括电平移位装置，其提供从第一电源电平到第二电压供应电平的电平移位。锁存器存储元件包括反馈栅极器件，当数据被写入锁存器输入级时，反馈栅极器件接收预定义的时钟信号以对门锁反馈到锁存器输入级。

17. 发明授权

US07505340B1 Method for implementing SRAM cell write performance evaluation 失效
标题翻译：实现SRAM单元写入性能评估的方法
公开(公告)号：US07505340B1
公开(公告)日：2009-03-17
申请号：US11845866
申请日：2007-08-28
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method implements static random access memory (SRAM) cell write performance evaluation. A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：一种方法实现了静态随机存取存储器（SRAM）单元写入性能评估。 SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

18. 发明申请

US20090063912A1 Method and Apparatus for Implementing SRAM Cell Write Performance Evaluation 失效
标题翻译：实现SRAM单元写入性能评估的方法和装置
公开(公告)号：US20090063912A1
公开(公告)日：2009-03-05
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/08
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：一种用于实现静态随机存取存储器（SRAM）单元写入性能评估的方法和装置，以及设置有主题电路所在的设计结构。 ASRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

19. 发明申请

US20090059697A1 METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写性能评估的方法和装置
公开(公告)号：US20090059697A1
公开(公告)日：2009-03-05
申请号：US11845866
申请日：2007-08-28
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。控制信号被施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

20. 发明授权

US07751266B2 High performance read bypass test for SRAM circuits 失效
标题翻译： SRAM电路的高性能读取旁路测试
公开(公告)号：US07751266B2
公开(公告)日：2010-07-06
申请号：US12146777
申请日：2008-06-26
申请人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Derick Gardner Behrends , Daniel Mark Nelson , Jeffrey Milton Scherer
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C11/41 , G11C29/1201
摘要： A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构和用于BIST（内置自检）的高性能SRAM（静态随机存取存储器）读取旁路的集成电路。该设计结构和集成结构包括用于SRAM阵列的读取输出的动态到静态转换单元和集成到动态到静态转换单元中的测试旁路单元，以便允许SRAM阵列的读取输出通过在不影响性能的非测试模式下，并绕过SRAM阵列的读取输出，并允许测试信号在测试模式下通过。

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