专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

12. 发明授权

US07023740B1 Substrate bias for programming non-volatile memory 有权
标题翻译：用于编程非易失性存储器的衬底偏置
公开(公告)号：US07023740B1
公开(公告)日：2006-04-04
申请号：US10755979
申请日：2004-01-12
申请人： Nga-Ching Wong , Darlene G. Hamilton
发明人： Nga-Ching Wong , Darlene G. Hamilton
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.
摘要翻译：用于编程非易失性存储器的衬底偏置的方法和系统。在包括用于非易失性存储单元的沟道区的阱下的深阱结构中施加偏置电压。在编程期间，施加到深阱的负偏压有利地在通道区域内产生电子的不均匀分布，在通道区域的表面具有大量电子。向控制栅极和漏极施加额外的偏置电压可能导致电子从沟道区迁移到非易失性存储单元的存储层。有利地，由于在通道区域的表面处的电子供应增加，非易失性电池的编程比常规技术更快。

13. 发明授权

US06944057B1 Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference 有权
标题翻译：使用温度依赖电压参考获得温度独立程序阈值电压分布的方法
公开(公告)号：US06944057B1
公开(公告)日：2005-09-13
申请号：US10431065
申请日：2003-05-06
申请人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
发明人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/10
摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.
摘要翻译：描述了一种用于控制存储器件中的栅极电压的方法。该方法包括提供适于与存储器件耦合的电路。该电路用于产生参考电压。该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。电压具有对应于存储器件的温度的值。该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

14. 发明授权

US06788583B2 Pre-charge method for reading a non-volatile memory cell 失效
标题翻译：用于读取非易失性存储单元的预充电方法
公开(公告)号：US06788583B2
公开(公告)日：2004-09-07
申请号：US10307749
申请日：2002-12-02
申请人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
发明人： Yi He , Edward F. Runnion , Zhizheng Liu , Mark W. Randolph , Darlene G. Hamilton , Pauling Chen , Binh Le
IPC分类号： G11C1606
CPC分类号： G11C7/12 , G11C16/0475 , G11C16/24
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.
摘要翻译：一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域线。将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

15. 发明授权

US06775187B1 Method of programming a dual cell memory device 失效
标题翻译：编程双单元存储器件的方法
公开(公告)号：US06775187B1
公开(公告)日：2004-08-10
申请号：US10422489
申请日：2003-04-24
申请人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
发明人： Darlene G. Hamilton , Edward F. Runnion , Edward Hsia , Kulachet Tanpairoj
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475
摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.
摘要翻译：一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。如果不是，则可以用标准编程脉冲编程第二电荷存储单元。如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

16. 发明授权

US06579781B1 Elimination of n+ contact implant from flash technologies by replacement with standard double-diffused and n+ implants 有权
标题翻译：通过更换标准双扩散和n +植入物来消除闪存技术中的n +接触植入物
公开(公告)号：US06579781B1
公开(公告)日：2003-06-17
申请号：US09619231
申请日：2000-07-19
申请人： Darlene G. Hamilton , Len Toyoshiba
发明人： Darlene G. Hamilton , Len Toyoshiba
IPC分类号： H01L21425
CPC分类号： H01L21/823814 , H01L27/1052
摘要： A method of manufacturing a semiconductor device that eliminates the n+ contact implant by using double diffused implants under the core cell contacts by forming core, n-channel and p-channel transistors in a semiconductor substrate, simultaneously forming source and drain DDI implants for the core transistors, forming source and drain Mdd implants for the core transistors, forming source and drain Pldd implants for the p-channel transistors, forming source and drain Nldd implants for the n-channel transistors, forming sidewall spacers on the core, n-channel and p-channel transistors, forming N+ implants for the n-channel transistors, forming P+ implants for the p-channel transistors and forming P+ contact implants for the p-channel transistors.
摘要翻译：一种制造半导体器件的方法，其通过在半导体衬底中形成芯，n沟道和p沟道晶体管，通过在核心单元触点下使用双扩散注入来消除n +接触注入，同时形成用于芯的源极和漏极DDI注入晶体管，为核心晶体管形成源极和漏极Mdd注入，形成用于p沟道晶体管的源极和漏极Pldd注入，为n沟道晶体管形成源极和漏极Nldd注入，在核心上形成侧壁间隔，n沟道和形成用于n沟道晶体管的N +注入，形成P沟道晶体管的P +注入，并形成P沟道晶体管的P +接触注入。

17. 发明授权

US06813752B1 Method of determining charge loss activation energy of a memory array 失效
标题翻译：确定存储器阵列的电荷损耗激活能的方法
公开(公告)号：US06813752B1
公开(公告)日：2004-11-02
申请号：US10306667
申请日：2002-11-26
申请人： Edward Hsia , Darlene G. Hamilton , Wei Zheng , Mark W. Randolph , Kulachet Tanpairoj
发明人： Edward Hsia , Darlene G. Hamilton , Wei Zheng , Mark W. Randolph , Kulachet Tanpairoj
IPC分类号： G06F1750
CPC分类号： G11C29/50 , G11C16/04
摘要： A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.
摘要翻译：确定存储器阵列的电荷损失激活的方法。存储器阵列被编程用于测试电荷损失的模式。然后，对于存储器阵列计算各自的烘烤时间，以在其各自的烘烤温度下经历给定量的电荷损失。然后，基于相应的烘烤时间计算电荷损失激活能。在一个版本中，通过在烘烤之前重复擦除和重新编程它们来循环存储器阵列。在另一个实施例中，存储器阵列的各个区域在烘烤之前被编程为多个不同的增量阈值电压。

18. 发明授权

US06799256B2 System and method for multi-bit flash reads using dual dynamic references 有权
标题翻译：使用双动态引用的多位闪存读取的系统和方法
公开(公告)号：US06799256B2
公开(公告)日：2004-09-28
申请号：US10136173
申请日：2002-05-01
申请人： Michael A. Van Buskirk , Darlene G. Hamilton , Pua-Ling Chen , Kazuhiro Kuribara
发明人： Michael A. Van Buskirk , Darlene G. Hamilton , Pua-Ling Chen , Kazuhiro Kuribara
IPC分类号： G11C1600
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5642 , G11C11/5671 , G11C16/0475 , G11C2211/5634
摘要： A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state or in an unprogrammed state.
摘要翻译：提供了用于正确读取存储器件中的多位存储器单元的系统和方法。使用第一参考单元和第二参考单元来确定平均动态参考值。通过读取第一参考单元的编程位并读取第二参考单元的未编程或擦除位来确定平均动态参考值来确定平均动态参考值。平均动态参考值可用于确定数据单元是处于编程状态还是处于未编程状态。

19. 发明授权

US06735114B1 Method of improving dynamic reference tracking for flash memory unit 有权
标题翻译：改进闪存单元动态参考跟踪的方法
公开(公告)号：US06735114B1
公开(公告)日：2004-05-11
申请号：US10357879
申请日：2003-02-04
申请人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
发明人： Darlene G. Hamilton , Eric M. Ajimine , Ming-Huei Shieh , Lee Cleveland , Edward F. Runnion , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/3418 , G11C16/0475 , G11C16/28
摘要： A method of programming a memory unit having a plurality of dual cell core memory devices and at least one dual cell dynamic reference device. The memory unit is subjected to an erase configuration operation such that each cell of the core memory devices is in a blank state and such that a threshold voltage of the at least one dynamic reference device is less than a charged program level threshold voltage. Thereafter, the at least one dynamic reference and the core memory devices are programmed using a page programming routine.
摘要翻译：一种编程具有多个双单元核心存储器件和至少一个双单元动态参考器件的存储器单元的方法。对存储器单元进行擦除配置操作，使得核心存储器件的每个单元处于空白状态，并且使得至少一个动态参考器件的阈值电压小于充电的程序电平阈值电压。此后，使用页面编程例程对至少一个动态参考和核心存储器设备进行编程。

20. 发明授权

US06707078B1 Dummy wordline for erase and bitline leakage 有权
标题翻译：用于擦除和位线泄漏的虚拟字线
公开(公告)号：US06707078B1
公开(公告)日：2004-03-16
申请号：US10230729
申请日：2002-08-29
申请人： Hidehiko Shiraiwa , Yider Wu , Jean Yee-Mei Yang , Mark T. Ramsbey , Darlene G. Hamilton
发明人： Hidehiko Shiraiwa , Yider Wu , Jean Yee-Mei Yang , Mark T. Ramsbey , Darlene G. Hamilton
IPC分类号： H01L2968
CPC分类号： H01L27/11568 , G11C16/0466 , H01L27/115
摘要： One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.
摘要翻译：本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不在开关状态之间循环。本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式