专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5953626A Dissolvable dielectric method 失效
标题翻译：溶解介电法
公开(公告)号：US5953626A
公开(公告)日：1999-09-14
申请号：US659166
申请日：1996-06-05
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

12. 发明授权

US5854515A Integrated circuit having conductors of enhanced cross-sectional area 失效
公开(公告)号：US5854515A
公开(公告)日：1998-12-29
申请号：US685143
申请日：1996-07-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L23/522 , H01L23/528 , H01L23/52
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

13. 发明授权

US5854131A Integrated circuit having horizontally and vertically offset interconnect lines 失效
标题翻译：集成电路具有水平和垂直偏移的互连线
公开(公告)号：US5854131A
公开(公告)日：1998-12-29
申请号：US655245
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H01L21/44
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间电介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

14. 发明授权

US5847462A Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 失效
标题翻译：集成电路具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US5847462A
公开(公告)日：1998-12-08
申请号：US748812
申请日：1996-11-14
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： An interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

15. 发明授权

US5827776A Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines 失效
标题翻译：制造集成电路的方法，其使用蚀刻停止件来产生交错的互连线
公开(公告)号：US5827776A
公开(公告)日：1998-10-27
申请号：US959106
申请日：1997-10-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/768 , H01L21/76816 , H01L23/5226 , H01L2924/0002
摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.
摘要翻译：提供了多层互连结构。多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。三个导体中的两个导体在单独的垂直和水平平面中彼此交错。第三导体有利地在两个第二导体的至少一部分之间隔开横向距离。第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

16. 发明授权

US5783481A Semiconductor interlevel dielectric having a polymide for producing air gaps 失效
标题翻译：具有用于产生气隙的聚酰亚胺的半导体层间电介质
公开(公告)号：US5783481A
公开(公告)日：1998-07-21
申请号：US659167
申请日：1996-06-05
申请人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
发明人： William S. Brennan , Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L21/48
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L2924/0002
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between horizontal or vertical spaced conductors. The dielectric is deposited upon a polyimide, wherein the polyimide is placed over and between an underlying level of conductors. As the overlying dielectric is deposited on the polyimide, the polyimide material outgasses to form air separation between the polyimide and dielectric. Air separation is particularly prevalent in regions between closely spaced conductors and in high elevational areas directly above each conductor. The dielectric deposition process preferably includes two deposition cycles. A first deposition temperature is used to force significant outgassing, and a second deposition cycle is needed to close any and all keyhole openings which might exist between closely spaced conductors. A combination of polyimide, air gaps (air-filled cavities) and deposited dielectric forms an inter-level dielectric structure having a low dielectric permittivity or dielectric constant in critical conductor spaces.
摘要翻译：提供介电材料，其具有在水平或垂直间隔的导体之间的介电沉积期间形成的气隙。电介质沉积在聚酰亚胺上，其中聚酰亚胺被放置在下面的导体层之上和之间。当覆盖的电介质沉积在聚酰亚胺上时，聚酰亚胺材料脱气形成聚酰亚胺和电介质之间的空气分离。空气分离在紧密间隔的导体之间的区域和每个导体正上方的高高度区域中是特别普遍的。介电沉积工艺优选包括两个沉积循环。使用第一沉积温度来强制显着的除气，并且需要第二沉积循环来封闭可能存在于紧密间隔的导体之间的任何和所有键孔。聚酰亚胺，气隙（充气腔）和沉积的电介质的组合形成在临界导体空间中具有低介电常数或介电常数的层间电介质结构。

17. 发明授权

US06208015B1 Interlevel dielectric with air gaps to lessen capacitive coupling 失效
标题翻译：具有气隙的间隔电介质以减少电容耦合
公开(公告)号：US06208015B1
公开(公告)日：2001-03-27
申请号：US09014192
申请日：1998-01-27
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L2358
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.
摘要翻译：布置在两层互连之间的半导体器件中的介电常数介电层的介电常数降低。电介质包括第一电介质层，优选地来自沉积在第一级互连上的硅烷源，以在相邻的第一互连结构之间的中点处形成气隙;第二电介质，其以间隔开的间隔跨越第二电介质包含气隙沟槽，以及形成的第三电介质在所述第二电介质上。在第三电介质上形成第二互连电平。

18. 发明授权

US6127264A Integrated circuit having conductors of enhanced cross-sectional area 有权
标题翻译：集成电路具有增强的横截面积的导体
公开(公告)号：US6127264A
公开(公告)日：2000-10-03
申请号：US166463
申请日：1998-10-05
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L23/522 , H01L23/528 , H01L21/4763 , H01L21/44 , H01L23/48
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

19. 发明授权

US6054356A Transistor and process of making a transistor having an improved LDD masking material 失效
标题翻译：晶体管和制造具有改进的LDD掩模材料的晶体管的工艺
公开(公告)号：US6054356A
公开(公告)日：2000-04-25
申请号：US761332
申请日：1996-12-10
申请人： Robert Dawson , Mark W. Michael , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , Fred N. Hause
IPC分类号： H01L21/266 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66598 , H01L21/266 , H01L29/6659 , H01L29/7833
摘要： A transistor is provided with a gradually increasing source and drain arsenic doping profile in a lateral direction from the gate conductor sidewall surfaces. The very smooth doping profile ensures small electric fields at the channel-drain interface for the benefit of reducing hot-carrier effects. Such a doping profile may be achieved by performing the ion implantation through a non-conformal layer of spin-on glass. By controlling the viscosity of the SOG and its deposition speed, different meniscus shapes may be formed. The doping profile of the arsenic in the source and drain regions follows the profile of the upper surface of the SOG. Arsenic is advantageously used for both the lightly doped and heavily doped regions of the source/drain junctions. Arsenic has lower mobility compared to phosphorus and is better at maintaining its original doping profile in heating of the device during further processing. Too much alteration in the original doping profile over time may change the device characteristics beyond acceptable levels.
摘要翻译：晶体管在栅极导体侧壁表面的横向上设置有逐渐增加的源极和漏极砷掺杂分布。非常平滑的掺杂分布确保了通道 - 漏极界面的小电场，有利于减少热载流子效应。这种掺杂分布可以通过通过旋涂玻璃的非保形层进行离子注入来实现。通过控制SOG的粘度及其沉积速度，可以形成不同的弯液面形状。源极和漏极区域中的砷的掺杂分布遵循SOG的上表面的轮廓。砷有利地用于源极/漏极结的轻掺杂区域和重掺杂区域。砷与磷相比具有较低的迁移率，并且在进一步加工期间更好地保持其在加热装置中的原始掺杂特性。随着时间的推移，原始掺杂特性的变化可能会将器件特性改变为可接受的水平。

20. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式