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11. 发明授权

US5426566A Multichip integrated circuit packages and systems 失效
标题翻译：多芯片集成电路封装和系统
公开(公告)号：US5426566A
公开(公告)日：1995-06-20
申请号：US826
申请日：1993-01-04
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Howard L. Kalter , Gordon A. Kelley, Jr. , Christopher P. Miller , Dale E. Pontius , Willem B. van der Hoeven , Steven Platt
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Howard L. Kalter , Gordon A. Kelley, Jr. , Christopher P. Miller , Dale E. Pontius , Willem B. van der Hoeven , Steven Platt
IPC分类号： H01L23/52 , H01L25/065 , H05K7/00
CPC分类号： H01L25/0657 , H01L25/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06596 , H01L2924/0002 , H01L2924/16195
摘要： Multichip integrated circuit packages and systems of multichip packages having reduced interconnecting lead lengths are disclosed. The multichip package includes a multiplicity of semiconductor chip layers laminated together in a unitized module. A first metallization pattern is connected to the integrated circuit chips on at least one side surface of the unitized module. In addition, at least one end surface of the module contains a second metallization pattern which is configured to facilitate connection of the package to an external signal source, such as another multichip package. The system includes at least two such packages which are electrically coupled via either metallization patterns provided on the end surface of the packagers. If required, a plurality of multichip packages can be directly coupled into the system in an analogous manner. Further specific details of the multichip package and the system of multichip packages are set forth herein.
摘要翻译：公开了具有减小的互连引线长度的多芯片集成电路封装和多芯片封装的系统。多芯片封装包括在单元化模块中层叠在一起的多个半导体芯片层。第一金属化图案在集成模块的至少一个侧表面上连接到集成电路芯片。此外，模块的至少一个端面包含第二金属化图案，其被配置为便于将封装件连接到诸如另一多芯片封装的外部信号源。该系统包括至少两个这样的包装，其经由设置在包装机的端面上的金属化图案电耦合。如果需要，可以以类似的方式将多个多芯片封装直接耦合到系统中。本文阐述了多芯片封装和多芯片封装系统的进一步具体细节。

12. 发明授权

US06882583B2 Method and apparatus for implementing DRAM redundancy fuse latches using SRAM 失效
标题翻译：使用SRAM实现DRAM冗余保险丝锁存器的方法和装置
公开(公告)号：US06882583B2
公开(公告)日：2005-04-19
申请号：US10249682
申请日：2003-04-30
申请人： Kevin W. Gorman , Dale E. Pontius
发明人： Kevin W. Gorman , Dale E. Pontius
IPC分类号： G11C5/00 , G11C7/00 , G11C29/00
CPC分类号： G11C29/802
摘要： A method and structure is disclosed for serially storing and retrieving fuse information to and from a non-scannable static random access memory (SRAM) array within an embedded DRAM structure. The SRAM array is part of a scan chain and is connected to upstream and downstream latches that make up the scan chain. Various data is serially scanned into the scan chain. As the data flows through the entire scan chain, the invention counts the number of bits scanned into the embedded DRAM structure using a counter. The counter can be included within the embedded DRAM structure. After the counter counts to an amount equal to the number of bits of storage of all downstream scan latches in the scan chain, the invention loads the fuse information into a shift register. When the shift register is full, the invention loads the contents of the shift register to a SRAM line. The lengths of the shift register and the SRAM line are equal to a fuse word. The invention repeats these processes of loading the shift register and loading the SRAM array until the SRAM array is full. The fuse information is read from the SRAM array by simply specifying an address in the SRAM array.
摘要翻译：公开了一种方法和结构，用于将嵌入式DRAM结构中的非可扫描静态随机存取存储器（SRAM）阵列中的熔丝信息串行存储和检索。 SRAM阵列是扫描链的一部分，并连接到构成扫描链的上游和下游锁存器。各种数据被串行扫描到扫描链中。当数据流经整个扫描链时，本发明使用计数器对扫描到嵌入式DRAM结构中的位数进行计数。计数器可以包含在嵌入式DRAM结构中。在计数器计数到等于扫描链中所有下游扫描锁存器的存储位数的量之后，本发明将熔丝信息加载到移位寄存器中。当移位寄存器满时，本发明将移位寄存器的内容加载到SRAM线。移位寄存器和SRAM线的长度等于保险丝字。本发明重复加载移位寄存器并加载SRAM阵列的这些过程，直到SRAM阵列充满。通过简单地指定SRAM阵列中的地址，从SRAM阵列读取熔丝信息。

13. 发明授权

US06674676B1 Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture 有权
标题翻译：用于微电池嵌入式DRAM（e-DRAM）架构的列冗余系统和方法
公开(公告)号：US06674676B1
公开(公告)日：2004-01-06
申请号：US10444226
申请日：2003-05-23
申请人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
发明人： Louis Lu-Chen Hsu , Gregory Fredeman , Chorng-Lii Hwang , Toshiaki Kirihata , Dale E. Pontius
IPC分类号： G11C700
CPC分类号： G11C29/846 , G11C2207/104
摘要： A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.
摘要翻译：一种列冗余系统，包括用于执行各个微单元内的列元素的冗余交换操作的列冗余设备。列冗余装置还包括熔丝信息存储装置，第一存储体地址解码机构对与读取操作相关的第一微小区对应的读存储体地址进行解码，第二存储体地址解码机构对与访问用于写操作的第二微小区。如果存在包含在第一微单元内的至少一个有缺陷的列元素，则列冗余设备生成与第一微单元中的至少一个缺陷列元素对应的内部列地址。类似地，如果在第二微小区内包含至少一个有缺陷的列元素，则列冗余设备产生对应于第二微小区中的至少一个缺陷列元素的内部列地址。

14. 发明授权

US6088206A Clamp circuit to limit overdrive of off chip driver 失效
标题翻译：钳位电路限制片外驱动器的超速
公开(公告)号：US6088206A
公开(公告)日：2000-07-11
申请号：US60837
申请日：1998-04-15
申请人： Francis Chan , Dale E. Pontius , Michael A. Roberge , Endre P. Thoma , Minh H. Tong
发明人： Francis Chan , Dale E. Pontius , Michael A. Roberge , Endre P. Thoma , Minh H. Tong
IPC分类号： H03K17/16 , H02H3/20
CPC分类号： H03K17/166
摘要： An off-chip driver (OCD) circuit including a clamp circuit to limit overdrive is provided. The circuit comprises an input signal which is inverted to provide an output signal. The driver circuit is comprised of a source-follower transistor to pull-down the output signal. The clamp circuit actively feeds back the source-follower potential to slow down the OCD and minimize ground bounce and noise that causes circuits to fail and signal integrity to be corrupted. The simple drive and clamp circuit is comprised of three transistors, one resistor, and one capacitor. The OCD slew rate is controlled by a current source and provides an output that changes between a positive voltage and ground. The circuit limits dv/dt without using a large resistor as a source follower, hence minimizing the adverse effect on performance.
摘要翻译：提供了包括限制过驱动的钳位电路的片外驱动器（OCD）电路。电路包括一个反相输入信号以提供输出信号。驱动器电路由源极跟随器晶体管组成，用于下拉输出信号。钳位电路主动反馈源跟随器电位以减慢OCD并最小化导致电路故障并且信号完整性损坏的接地反弹和噪声。简单的驱动和钳位电路由三个晶体管，一个电阻器和一个电容器组成。 OCD压摆率由电流源控制，并提供在正电压和地之间变化的输出。电路限制dv / dt，而不使用大电阻作为源极跟随器，从而最小化对性能的不利影响。

15. 发明授权

US5920222A Tunable pulse generator based on a wave pipeline 失效
标题翻译：基于波导管道的可调脉冲发生器
公开(公告)号：US5920222A
公开(公告)日：1999-07-06
申请号：US839219
申请日：1997-04-22
申请人： Steven M. Eustis , Dale E. Pontius
发明人： Steven M. Eustis , Dale E. Pontius
IPC分类号： H03K5/15 , H03K5/14
CPC分类号： H03K5/15046
摘要： A pulse generator comprising a delay circuit uses a series of "n" delay stages to generate pulses that do not have distorted duty cycles. The output of the delay stage "n" feeds back to reset the delay stage "n-2". The output of each of the delay stages initially changes from a first logic state to a second logic stage at the leading edge of a pulse. The output of each delay stage switches back to the first logic state, or the trailing edge of the pulse, upon receipt of the feedback signal from a subsequent delay stage. The wave characteristics depend only on the rising edge of the pulse because the rising edge of the pulse of a future stage generates the falling edge of the current stage.
摘要翻译：包括延迟电路的脉冲发生器使用一系列“n”个延迟级产生不具有失真占空比的脉冲。延迟级“n”的输出反馈到复位延迟级“n-2”。每个延迟级的输出在脉冲的前沿开始从第一逻辑状态改变到第二逻辑级。当接收到来自后续延迟级的反馈信号时，每个延迟级的输出切换回到第一逻辑状态或脉冲的后沿。波特性仅取决于脉冲的上升沿，因为未来级的脉冲的上升沿会产生当前级的下降沿。

16. 发明授权

US5905395A Miller effect-based delay circuit 失效
标题翻译：基于米勒效应的延迟电路
公开(公告)号：US5905395A
公开(公告)日：1999-05-18
申请号：US837858
申请日：1997-04-22
申请人： Dale E. Pontius
发明人： Dale E. Pontius
IPC分类号： H03K5/13 , H03K5/14
CPC分类号： H03K5/133
摘要： A delay circuit which employs a Miller effect to delay a signal while driving a subsequent amplifier stage. The Miller effect is dependent upon loading of the circuits on an integrated circuit upon which the delay circuit is implemented, which allows the delay circuit to compensate its delay in relation to other process variation delays present on the integrated circuit. The delay circuit has a first delay stage which delays an input signal and drives a second stage. The delay circuit incorporates a dummy drive stage which adds loading to the first delay stage. In addition, the dummy stage experiences dynamic loading of the delay chain between the first and second stages which allows the coupling of the effect of this dynamic loading back to the first stage through the Miller effect.
摘要翻译：延迟电路采用米勒效应来延迟信号，同时驱动后续放大器级。米勒效应取决于在实现延迟电路的集成电路上加载电路，这允许延迟电路相对于存在于集成电路上的其它过程变化延迟补偿其延迟。延迟电路具有延迟输入信号并驱动第二级的第一延迟级。延迟电路包括将负载加载到第一延迟级的虚拟驱动级。此外，虚拟阶段经历第一和第二阶段之间的延迟链的动态加载，这允许通过米勒效应将该动态加载的效果耦合回第一阶段。

17. 发明授权

US5614846A Latch circuit with state-walk logic 失效
标题翻译：具有状态行为逻辑的锁存电路
公开(公告)号：US5614846A
公开(公告)日：1997-03-25
申请号：US548632
申请日：1995-10-26
申请人： Dale E. Pontius
发明人： Dale E. Pontius
IPC分类号： G11C11/408 , H03K3/012 , H03K3/037 , H03K19/096
CPC分类号： H03K3/012 , G11C11/408 , G11C11/4082 , H03K3/037
摘要： A latch circuit employs state-walk logic that makes the transition from "set" to "latched" states without the need for multiple phases, critical timing or introduction of extra periods into any timings to account for worst case scenarios. The has particular application to row address receivers for dynamic random access memories (DRAMs) and, in its basic form, comprises a pair of identical receiver circuits of opposite logic state when off, with clock and data inputs and true and complementary outputs. The receivers are turned on by an activating clock signal. When the receivers are enabled, address data is evaluated as soon as it is received causing the latch to be set. This is the first step in the "state walk" of the latch. The outputs of the latch are fed back to turn off the receiver circuits completing the second step of the "state walk". The circuit now ignores any changes in the input address data, thus latching the input data.
摘要翻译：锁存电路采用状态行为逻辑，其使得从“设置”转换到“锁存”状态，而不需要多个阶段，关键时序或将任何时间段引入任何时间以解决最坏情况。具有用于动态随机存取存储器（DRAM）的行地址接收器的特殊应用，并且在其基本形式中包括一对相同逻辑状态的相同的接收器电路，其具有时钟和数据输入以及真实和互补的输出。接收器通过激活时钟信号接通。当接收器被使能时，一旦接收到地址数据，就会对其进行评估，使锁存器被置位。这是闩锁“国家步行”的第一步。反馈锁存器的输出以关闭完成“状态行进”第二步骤的接收器电路。该电路现在忽略输入地址数据的任何变化，从而锁定输入数据。

18. 发明授权

US5430679A Flexible redundancy architecture and fuse download scheme 失效
标题翻译：灵活的冗余架构和保险丝下载方案
公开(公告)号：US5430679A
公开(公告)日：1995-07-04
申请号：US119797
申请日：1993-09-10
申请人： Nathan R. Hiltebeitel , Dale E. Pontius , Steven W. Tomashot
发明人： Nathan R. Hiltebeitel , Dale E. Pontius , Steven W. Tomashot
IPC分类号： G06F11/16 , G06F12/16 , G11C29/00 , G11C29/04 , H01H85/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/808
摘要： A fuse download system for programming decoders for redundancy. Auxiliary fuse banks have sets of fuses that store logic states that (a) select a redundant decoder and (b) indicate the address of a faulty row/column of memory cells. When the chip is first powered up, each set of fuses is accessed and downloaded to program selected redundant decoders. Because the fuse sets can be dynamically assigned to redundant decoders on an any-for-any basis, the fault tolerance of the redundancy system is enhanced.
摘要翻译：用于冗余编程解码器的熔丝下载系统。辅助保险丝组有一组保险丝，存储逻辑状态，（a）选择冗余解码器，（b）指示存储器单元故障行/列的地址。当芯片首次通电时，每组保险丝被访问并下载到程序中选择的冗余解码器。由于可以在任何情况下将熔丝组动态分配给冗余解码器，故冗余系统的容错能力得到提高。

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