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11. 发明申请

US20060240650A1 Semiconductor device having a plurality of different layers and method therefor 有权
标题翻译：具有多个不同层的半导体器件及其方法
公开(公告)号：US20060240650A1
公开(公告)日：2006-10-26
申请号：US11111451
申请日：2005-04-21
申请人： Marius Orlowski , Vance Adams
发明人： Marius Orlowski , Vance Adams
IPC分类号： H01L21/425 , H01L29/768 , H01L27/148 , H01L29/74
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/78 , H01L29/7846 , H01L29/7848
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译：可以使用具有选定的弹性模量的材料实现机械应力控制。这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。这些方法中的任何一种或多种可以组合使用。机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。

12. 发明申请

US20060194384A1 SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开
标题翻译：具有多个半导体层的半导体器件
公开(公告)号：US20060194384A1
公开(公告)日：2006-08-31
申请号：US11382432
申请日：2006-05-09
申请人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
发明人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203
摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.
摘要翻译：半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的迁移率。用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。或者，晶面可以是（111），在这种情况下的取向是不重要的。用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

13. 发明申请

US20060172468A1 Method of making a planar double-gated transistor 有权
标题翻译：制造平面双门控晶体管的方法
公开(公告)号：US20060172468A1
公开(公告)日：2006-08-03
申请号：US11047448
申请日：2005-01-31
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L21/00 , H01L21/84 , H01L21/331 , H01L21/8222
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66628 , H01L29/78648
摘要： A silicon layer interposed between the top silicon nitride layer (SiN) and a silicon germanium layer (SiGe) which in turn is over a thick oxide (BOX) is selectively etched to leave a stack with a width that sets the gate length. A sidewall insulating layer is formed on the SiGe layer leaving the sidewall of the Si layer exposed. Silicon is epitaxially grown from the exposed silicon sidewall to form in-situ-doped silicon source/drain regions. The nitride layer is removed using the source/drain regions as a boundary for an upper gate location. The source/drain regions are coated with a dielectric. The SiGe layer is removed to provide a lower gate location. Both the upper and lower gate locations are filled with metal to form upper and lower gates for the transistor.
摘要翻译：插入在顶部氮化硅层（SiN）和再次在厚氧化物（BOX）之上的硅锗层（SiGe）之间的硅层被选择性地蚀刻以留下具有设定栅极长度的宽度的堆叠。在SiGe层上形成侧壁绝缘层，离开Si层的侧壁露出。硅从暴露的硅侧壁外延生长以形成原位掺杂的硅源/漏区。使用源极/漏极区域作为上部栅极位置的边界去除氮化物层。源极/漏极区域涂覆有电介质。 SiGe层被去除以提供较低的栅极位置。上部和下部栅极位置都用金属填充，以形成晶体管的上部和下部栅极。

14. 发明申请

US20060166492A1 Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
标题翻译：采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺
公开(公告)号：US20060166492A1
公开(公告)日：2006-07-27
申请号：US11043577
申请日：2005-01-26
申请人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
发明人： Marius Orlowski , Vance Adams , Chun-Li Liu , Matthew Stoker
IPC分类号： H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译：半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

15. 发明申请

US20050215008A1 Method for forming a semiconductor device having a notched control electrode and structure thereof 有权
标题翻译：用于形成具有切口控制电极的半导体器件及其结构的方法
公开(公告)号：US20050215008A1
公开(公告)日：2005-09-29
申请号：US10811461
申请日：2004-03-26
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/28114
摘要： A method for forming a semiconductor device (10) includes providing a substrate (20) having a surface; forming an insulating layer (22) over the surface of the substrate (20); forming a first patterned conductive layer (30) over the-insulating layer (22); forming a second patterned conductive layer (32) over the first patterned conductive layer (30); forming a patterned non-insulating layer (34) over the second patterned conductive layer (32); and selectively removing portions of the first and second patterned conductive layers (30, 32) to form a notched control electrode for the semiconductor device (10).
摘要翻译：一种形成半导体器件（10）的方法包括提供具有表面的衬底（20）; 在所述衬底（20）的表面上形成绝缘层（22）; 在所述绝缘层（22）上形成第一图案化导电层（30）; 在所述第一图案化导电层（30）上形成第二图案化导电层（32）; 在所述第二图案化导电层（32）上形成图案化的非绝缘层（34）; 以及选择性地去除所述第一和第二图案化导电层（30,32）的部分以形成用于所述半导体器件（10）的切口控制电极。

16. 发明授权

US5506161A Method of manufacturing graded channels underneath the gate electrode extensions 失效
标题翻译：在栅电极延伸部下方制造分级通道的方法
公开(公告)号：US5506161A
公开(公告)日：1996-04-09
申请号：US328317
申请日：1994-10-24
申请人： Marius Orlowski , Shih K. Cheng
发明人： Marius Orlowski , Shih K. Cheng
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66492 , H01L21/823807 , H01L29/1045 , H01L29/1083 , H01L29/66575 , H01L29/66659 , H01L29/7836
摘要： Insulated gate semiconductor device (10) and a method of manufacturing the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) includes an N-channel transistor (55) and a P-channel transistor (60). The N-channel transistor (55) has a gate electrode (22') that has a central portion (22) and gate electrode extensions (41) adjacent to the central portion (22). Likewise the P-channel transistor (60) has a gate electrode (24') that has a central portion (24) and gate electrode extensions (42) adjacent to the central portion (24). The gate electrode extensions (41, 42) are formed by filling openings (34, 36) with a gate electrode material. The openings are used for the formation of graded channel regions underneath the gate electrode extensions (41, 42).
摘要翻译：绝缘栅半导体器件（10）和绝缘栅半导体器件（10）的制造方法。绝缘栅半导体器件（10）包括N沟道晶体管（55）和P沟道晶体管（60）。 N沟道晶体管（55）具有栅电极（22'），其具有与中心部分（22）相邻的中心部分（22）和栅电极延伸部分（41）。类似地，P沟道晶体管（60）具有栅电极（24'），其具有与中心部分（24）相邻的中心部分（24）和栅电极延伸部分（42）。通过用栅电极材料填充开口（34,36）形成栅电极延伸部（41,42）。这些开口用于在栅电极延伸部（41,42）下形成渐变沟道区。

17. 发明申请

US20190058120A1 Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses 审中-公开
公开(公告)号：US20190058120A1
公开(公告)日：2019-02-21
申请号：US16168678
申请日：2018-10-23
申请人： Marius Orlowski , Gargi Ghosh , Anshuman Verma
发明人： Marius Orlowski , Gargi Ghosh , Anshuman Verma
IPC分类号： H01L45/00 , H01L27/24
摘要： A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse.

18. 发明授权

US08158484B2 Method of forming an inverted T shaped channel structure for an inverted T channel field effect transistor device 有权
标题翻译：形成用于反向T沟道场效应晶体管器件的反相T形沟道结构的方法
公开(公告)号：US08158484B2
公开(公告)日：2012-04-17
申请号：US12679385
申请日：2007-10-03
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7854 , H01L29/66795 , H01L29/78687
摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate, and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.
摘要翻译：一种形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括提供半导体衬底，在半导体衬底上提供第一半导体材料的第一层，以及在所述第一层上提供第二半导体材料层。选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。该方法还包括根据不同的去除速率选择性地去除第一层的一部分和第二层的一部分，以便提供倒置的T形沟道结构的横向层和垂直沟道部分，并且去除横向层，以提供倒置的T形通道结构的水平通道部分。

19. 发明授权

US08071459B2 Method of sealing an air gap in a layer of a semiconductor structure and semiconductor structure 有权
标题翻译：密封半导体结构和半导体结构层中的气隙的方法
公开(公告)号：US08071459B2
公开(公告)日：2011-12-06
申请号：US12936113
申请日：2008-04-17
申请人： Greg Braeckelmann , Marius Orlowski , Andreas Wild
发明人： Greg Braeckelmann , Marius Orlowski , Andreas Wild
IPC分类号： H01L21/00
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76834
摘要： A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. In another embodiment, the at least one air gap extends from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces, and a barrier layer of a barrier dielectric material is formed over the exposed portions of the side surfaces of each of the at least two conductive lines.
摘要翻译：密封半导体结构层中的气隙的方法包括提供具有至少一个气隙的半导体结构的第一层，用于在形成在第一层中的至少两个导电线之间提供隔离。所述至少一个气隙从所述第一层的第一表面延伸到所述第一层中。该方法还包括在第一层的第一表面和至少一个气隙上形成阻挡介电材料的阻挡层。阻挡介电材料被选择为具有小于3.5的介电常数并且提供屏障以防止化学品进入至少一个气隙。在另一个实施例中，至少一个空气间隙从第一层的第一表面延伸到至少两个导电线的侧表面的至少一部分以暴露至少一部分侧表面，并且阻挡层在所述至少两根导电线中的每一个的侧表面的暴露部分上形成阻挡介电材料。

20. 发明申请

US20100311213A1 METHOD OF FORMING AN INVERTED T SHAPED CHANNEL STRUCTURE FOR AN INVERTED T CHANNEL FIELD EFFECT TRANSISTOR DEVICE 有权
标题翻译：形成用于反相T通道场效应晶体管器件的反相T形通道结构的方法
公开(公告)号：US20100311213A1
公开(公告)日：2010-12-09
申请号：US12679385
申请日：2007-10-03
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L21/336 , H01L21/302
CPC分类号： H01L29/7854 , H01L29/66795 , H01L29/78687
摘要： A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.
摘要翻译：形成具有用于反向T沟道场效应晶体管ITFET器件的垂直沟道部分和水平沟道部分的反向T形沟道结构的方法包括提供半导体衬底，在半导体衬底上提供第一半导体材料层，在所述第一层上提供第二半导体材料层。选择第一和第二半导体材料，使得第一半导体材料具有小于除去第二半导体材料的速率的去除速率。该方法还包括根据不同的去除速率选择性地去除第一层的一部分和第二层的一部分，以便提供倒置的T形沟道结构的横向层和垂直沟道部分，并且去除横向层，以提供倒置的T形通道结构的水平通道部分。

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