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1. 发明申请

US20050275018A1 Semiconductor device with multiple semiconductor layers 审中-公开
标题翻译：具有多个半导体层的半导体器件
公开(公告)号：US20050275018A1
公开(公告)日：2005-12-15
申请号：US10865351
申请日：2004-06-10
申请人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
发明人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203
摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.
摘要翻译：半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的载流子迁移率。用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。或者，晶面可以是（111），在这种情况下的取向是不重要的。用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

2. 发明申请

US20060194384A1 SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS 审中-公开
标题翻译：具有多个半导体层的半导体器件
公开(公告)号：US20060194384A1
公开(公告)日：2006-08-31
申请号：US11382432
申请日：2006-05-09
申请人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
发明人： Suresh Venkatesan , Mark Foisy , Michael Mendicino , Marius Orlowski
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203
摘要： A semiconductor device structure uses two semiconductor layers to separately optimize N and P channel transistor carrier mobility. The conduction characteristic for determining this is a combination of material type of the semiconductor, crystal plane, orientation, and strain. Hole mobility is improved in P channel transistors when the conduction characteristic is characterized by the semiconductor material being silicon germanium, the strain being compressive, the crystal plane being (100), and the orientation being . In the alternative, the crystal plane can be (111) and the orientation in such case is unimportant. The preferred substrate for N-type conduction is different from the preferred (or optimum) substrate for P-type conduction. The N channel transistors preferably have tensile strain, silicon semiconductor material, and a (100) plane. With the separate semiconductor layers, both the N and P channel transistors can be optimized for carrier mobility.
摘要翻译：半导体器件结构使用两个半导体层来分别优化N沟道晶体管和P沟道晶体管的迁移率。用于确定的导电特性是半导体的材料类型，晶面，取向和应变的组合。当导电特性的特征在于半导体材料为硅锗时，p型沟道晶体管的空穴迁移率得到改善，应变为压缩，晶面为（100），取向为100。或者，晶面可以是（111），在这种情况下的取向是不重要的。用于N型导电的优选衬底不同于用于P型导电的优选（或最佳）衬底。 N沟道晶体管优选具有拉伸应变，硅半导体材料和（100）平面。通过分开的半导体层，N沟道晶体管和P沟道晶体管都可以优化载流子迁移率。

3. 发明申请

US20060110892A1 Semiconductor process for forming stress absorbent shallow trench isolation structures 有权
标题翻译：用于形成应力吸收性浅沟槽隔离结构的半导体工艺
公开(公告)号：US20060110892A1
公开(公告)日：2006-05-25
申请号：US10996319
申请日：2004-11-22
申请人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
发明人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878
摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
摘要翻译：半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

4. 发明申请

US20070155073A1 Method of forming device having a raised extension region 有权
标题翻译：具有凸起延伸区域的成形装置的方法
公开(公告)号：US20070155073A1
公开(公告)日：2007-07-05
申请号：US11324510
申请日：2006-01-03
申请人： Sinan Goktepeli , Mark Foisy
发明人： Sinan Goktepeli , Mark Foisy
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , Y10S438/933
摘要： A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.
摘要翻译：公开了形成具有覆盖在化合物半导体层上的栅极结构的晶体管的延伸区域的方法。在深源极/漏极注入之前或之后使用退火将掺杂剂从与栅极结构相邻的凸起区域扩散到栅极结构下方的位置。当来自凸起区域的掺杂剂在深源/漏植入之前扩散时，可以使用非扩散激活过程来激活源极/漏极注入。

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