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11. 发明授权

US07429703B2 Methods and apparatus for integrated circuit device power distribution via internal wire bonds 有权
标题翻译：集成电路器件通过内部引线键分配电力的方法和装置
公开(公告)号：US07429703B2
公开(公告)日：2008-09-30
申请号：US10722652
申请日：2003-11-26
申请人： Kerry Leeds Davison , Donald Earl Hawk, Jr. , Yehuda Smooha
发明人： Kerry Leeds Davison , Donald Earl Hawk, Jr. , Yehuda Smooha
IPC分类号： H01R13/46 , H05K5/00
CPC分类号： H01L23/50 , H01L23/5286 , H01L24/02 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48 , H01L2224/49171 , H01L2924/00014 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/3025 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit device comprising a die having a top surface with a peripheral region and an interior region surrounded by the peripheral region. Bond pads are disposed in the peripheral region of the die. One or more internal buses are disposed in the interior region of the die. The one or more internal buses distribute power to internal node points of the die. One or more bond wires connect one or more peripheral bond pads with one or more internal buses.
摘要翻译：一种集成电路器件，包括具有顶表面与外围区域的模具以及由周边区域包围的内部区域。接合焊盘设置在管芯的周边区域。一个或多个内部总线设置在模具的内部区域中。一个或多个内部总线将功率分配给芯片的内部节点。一个或多个接合线将一个或多个外围接合焊盘与一个或多个内部总线连接。

12. 发明授权

US07145364B2 Self-bypassing voltage level translator circuit 有权
标题翻译：自我旁路电压电平转换电路
公开(公告)号：US07145364B2
公开(公告)日：2006-12-05
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.
摘要翻译：响应于控制信号，电压电平转换器电路可选择性地以至少两种模式之一工作。在第一模式中，电压电平转换器电路用于将提供第一电压的参考第一源的输入信号转换为参考提供第二电压的第二源的输出信号。在第二模式中，电压电平转换器电路用于提供从电压转换器电路的输入到其输出的信号路径，而不转换输入信号。控制信号表示第一电压和第二电压之间的差。

13. 发明授权

US07002372B2 Moderate current 5V tolerant buffer using a 2.5 volt power supply 有权
标题翻译：使用2.5伏电源的中等电流5V容限缓冲器
公开(公告)号：US07002372B2
公开(公告)日：2006-02-21
申请号：US10759162
申请日：2004-01-20
申请人： Carol Ann Huber , Bernard Lee Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Ann Huber , Bernard Lee Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00315 , H03K19/018521
摘要： A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.
摘要翻译：具有中等电流公差能力的低电压，5V容限开漏输出缓冲器采用3.3V技术，使用2.5V或更小的额定电源。缓冲器包括反相器，三个n沟道FET晶体管的电流路径的串联连接和背栅偏置发生器。三个晶体管的串联连接的一个端子连接到PAD，并且该串联的下部晶体管的另一个端子连接到地。偏置发生器使用在VDD和PAD之间交叉连接的两个p沟道场效应晶体管（FET）形成。三个晶体管的中心一个的栅极连接到电源。偏置发生器的输出端连接到上部晶体管的栅极。本发明的缓冲器可以使用标准的3.3V工艺制造，但是功率为例如2.5V或1.8V的电源。

14. 发明申请

US20050225912A1 Electrical over stress robustness 有权
标题翻译：电应力鲁棒性强
公开(公告)号：US20050225912A1
公开(公告)日：2005-10-13
申请号：US10821836
申请日：2004-04-12
申请人： Sandeep Pant , Gary Weiss , David Thompson , Yehuda Smooha
发明人： Sandeep Pant , Gary Weiss , David Thompson , Yehuda Smooha
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： Protection is provided against electrical surges resulting from Electrical Over Stress conditions, e.g., when interfacing circuits with powered connections. An EOS shunt is activated for as long as the EOS condition exists. EOS protection using an EOS shunt in accordance with the principles of the present invention remains activated by a voltage threshold trigger as long as necessary. In a disclosed embodiment, an EOS shunt includes a voltage threshold detector that detects a voltage on a power bus with respect to a ground rail exceeding a predetermined amount, e.g., 5 volts in a device powered at 3.3 volts. During the EOS event, a path between power and ground comprising a transistor is turned on.
摘要翻译：提供了防止由电过压条件引起的电涌，例如当与电源连接相连的电路时。只要EOS条件存在，EOS分流器就被激活。根据本发明的原理使用EOS分流器的EOS保护由需要的电压阈值触发保持激活。在公开的实施例中，EOS分流器包括电压阈值检测器，该电压阈值检测器相对于超过预定量的接地轨，例如在以3.3V供电的设备中检测5伏特的电力总线上的电压。在EOS事件期间，包括晶体管的电源和地之间的路径导通。

15. 发明授权

US06838769B1 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads 有权
标题翻译：双镶嵌结合垫结构，用于降低压力并允许垫下的电路
公开(公告)号：US06838769B1
公开(公告)日：2005-01-04
申请号：US09465089
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/40 , H01L23/52
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05546 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.
摘要翻译：接合焊盘位于集成电路器件内形成的有源电路上。阻挡膜形成接合焊盘开口的上部的底表面，其还包括延伸穿过底表面的通孔以形成双镶嵌结构。接合焊盘抵抗诸如开裂的应力作用，当将外部导线接合到接合焊盘时可以产生裂纹，因此防止接合焊盘和下面的电路之间的漏电流。

16. 发明授权

US06476472B1 Integrated circuit package with improved ESD protection for no-connect pins 有权
标题翻译：集成电路封装，具有改进的ESD保护，用于无连接引脚
公开(公告)号：US06476472B1
公开(公告)日：2002-11-05
申请号：US09641899
申请日：2000-08-18
申请人： Kerry L. Davison , Donald E. Hawk, Jr. , Yehuda Smooha
发明人： Kerry L. Davison , Donald E. Hawk, Jr. , Yehuda Smooha
IPC分类号： H01L2302
CPC分类号： H01L23/60 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： An integrated circuit (IC) package includes an IC having at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conductive traces, which are connected to respective bond pads of the IC, and a second plurality of conductive traces, which are not connected to any of the plurality of bond pads of the IC. Either the substrate or the IC has a common conductive trace that is connected to the ESD protection circuit. Each of the second plurality of conductive traces is connected to the common conductive trace.
摘要翻译：集成电路（IC）封装包括具有至少一个ESD保护电路的IC，其提供防止静电放电的保护。 IC具有多个不连接到ESD保护电路的接合焊盘。 IC连接到基板。衬底具有连接到IC的相应接合焊盘的第一多个导电迹线和不连接到IC的多个接合焊盘中的任一个的第二多个导电迹线。衬底或IC都具有连接到ESD保护电路的公共导电迹线。第二多个导电迹线中的每一个连接到公共导电迹线。

17. 发明授权

US06417087B1 Process for forming a dual damascene bond pad structure over active circuitry 有权
标题翻译：用于在有源电路上形成双镶嵌键合焊盘结构的工艺
公开(公告)号：US06417087B1
公开(公告)日：2002-07-09
申请号：US09465075
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2221/1036 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.
摘要翻译：用于在集成电路内形成双镶嵌键合焊盘的工艺产生接合焊盘，其抵抗应力作用并因此允许在有源电路上形成接合焊盘。该方法包括通过在开口的上部的底部表面上形成具有阻挡层膜的接合焊盘开口形成双镶嵌结构，以及形成向下延伸通过底表面的通孔。该工艺产生接合焊盘，其抵抗诸如当将外部电线接合到接合焊盘时可产生的应力作用的破坏。防止接合焊盘和底层电路之间的泄漏电流。

18. 发明申请

US20140040847A1 SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES 审中-公开
标题翻译：用于生成双模式技术的物理决定性边界互连特征的系统和方法
公开(公告)号：US20140040847A1
公开(公告)日：2014-02-06
申请号：US13564159
申请日：2012-08-01
申请人： John A. Milinichik , Yehuda Smooha , Daniel J. Delpero , Gregg R. Harleman , Scott N. Bertino
发明人： John A. Milinichik , Yehuda Smooha , Daniel J. Delpero , Gregg R. Harleman , Scott N. Bertino
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/70433 , G03F7/70466
摘要： One aspect provides a system for generating a layout for dual patterning technologies. In one embodiment, the system includes: (1) a deterministic boundary interconnect feature generator configured to generate a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and (2) cell placement and interconnect routing tools associated with the deterministic boundary interconnect feature generator and configured to place the deterministic boundary interconnect feature.
摘要翻译：一方面提供了一种用于生成用于双重图案化技术的布局的系统。在一个实施例中，系统包括：（1）确定性边界互连特征发生器，被配置为基于至少一个双图案设计规则为单元生成确定性边界互连特征; 和（2）与确定性边界互连特征生成器相关联的单元布置和互连路由工具，并且被配置成放置确定性边界互连特征。

19. 发明申请

US20100271118A1 I/O Buffer with Low Voltage Semiconductor Devices 失效
标题翻译：带低压半导体器件的I / O缓冲器
公开(公告)号：US20100271118A1
公开(公告)日：2010-10-28
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

20. 发明申请

US20080074171A1 Method and Apparatus for Improving Reliability of an Integrated Circuit Having Multiple Power Domains 有权
标题翻译：提高具有多个电源域的集成电路的可靠性的方法和装置
公开(公告)号：US20080074171A1
公开(公告)日：2008-03-27
申请号：US11535198
申请日：2006-09-26
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , H01L27/0251 , H03K19/00315
摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.
摘要翻译：具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

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