专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20070224795A1 DUMMY VIAS FOR DAMASCENE PROCESS 有权
标题翻译： DAMASCENE过程的DUMMY VIAS
公开(公告)号：US20070224795A1
公开(公告)日：2007-09-27
申请号：US11457032
申请日：2006-07-12
申请人： Kuei Shun CHEN , Chin-Hsiang LIN , Vencent CHANG , Lawrence LIN , Lai Chien WEN , Jhun Hua CHEN
发明人： Kuei Shun CHEN , Chin-Hsiang LIN , Vencent CHANG , Lawrence LIN , Lai Chien WEN , Jhun Hua CHEN
IPC分类号： H01L21/44
CPC分类号： H01L21/76811 , H01L21/76807 , H01L21/76813 , H01L21/7684 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).
摘要翻译：制造集成电路的方法包括在衬底上提供低k电介质层，低k电介质层包括或邻近多个导电特征; 图案化低k电介质层以形成沟槽; 图案化低k电介质层以形成导电通孔和虚拟通孔，其中每个导电通孔与多个导电特征中的至少一个对齐，并且至少一个沟槽，并且每个虚拟通孔是在多个导电特征之上的距离; 使用一种或多种导电材料填充沟槽，导电通孔和虚拟通孔; 并平坦化导电材料。

12. 发明申请

US20070091287A1 IMMERSION LITHOGRAPHY APPARATUS AND METHODS 有权
标题翻译：倾斜平面设备和方法
公开(公告)号：US20070091287A1
公开(公告)日：2007-04-26
申请号：US11427421
申请日：2006-06-29
申请人： Ching-Yu CHANG , Burn Jeng LIN , Chin-Hsiang LIN
发明人： Ching-Yu CHANG , Burn Jeng LIN , Chin-Hsiang LIN
IPC分类号： B08B3/12 , B08B7/00 , B08B3/00 , G03B27/52
CPC分类号： G03F7/70925 , G03F7/70341
摘要： A lithography apparatus includes an imaging lens module; a substrate table positioned underlying the imaging lens module and configured to hold a substrate; and a cleaning module adapted to clean the lithography apparatus. The cleaning module is selected from the group consisting of an ultrasonic unit, a scrubber, a fluid jet, an electrostatic cleaner, and combinations thereof.
摘要翻译：光刻设备包括成像透镜模块; 位于所述成像透镜模块下方且被配置为保持基板的基板台; 以及适于清洁光刻设备的清洁模块。清洁模块选自超声波单元，洗涤器，流体射流，静电清洁器及其组合。

13. 发明申请

US20130322990A1 LOADPORT BRIDGE FOR SEMICONDUCTOR FABRICATION TOOLS 有权
标题翻译：半导体制造工具的负载桥
公开(公告)号：US20130322990A1
公开(公告)日：2013-12-05
申请号：US13486024
申请日：2012-06-01
申请人： Shih-Hung CHEN , Ying XIAO , Chin-Hsiang LIN
发明人： Shih-Hung CHEN , Ying XIAO , Chin-Hsiang LIN
IPC分类号： H01L21/677
CPC分类号： H01L21/6773 , H01L21/67733 , H01L21/67775
摘要： A wafer handling system with apparatus for transporting wafers between semiconductor fabrication tools. In one embodiment, the apparatus is a loadport bridge mechanism including an enclosure having first and second mounting ends, a docking port at each end configured and dimensioned to interface with a loadport of a semiconductor tool, and at least one wafer transport robot operable to transport a wafer between the docking ports. The wafer transport robot hands off or receives a wafer to/from a tool robot at the loadports of a first and second tool. The bridge mechanism allows one or more wafers to be transferred between loadports of different tools on an individual basis without reliance on the FAB's automated material handling system (AMHS) for bulk wafer transport inside a wafer carrier such as a FOUP or others.
摘要翻译：一种具有用于在半导体制造工具之间传输晶片的装置的晶片处理系统。在一个实施例中，该装置是装载端口机构，其包括具有第一和第二安装端的外壳，每个端部处的对接端口被构造和尺寸设计成与半导体工具的承载端口相接合，以及至少一个可运输的晶片传送机械手在对接端口之间的晶片。晶片传送机器人在第一和第二工具的载荷端口移动或接收来自工具机器人的晶片。桥接机构允许一个或多个晶片在不同工具的载荷端口之间单独传输，而不依赖于FAB的自动化材料处理系统（AMHS），用于在诸如FOUP或其它晶片载体之间的体晶片传输。

14. 发明申请

US20130270454A1 SYSTEM AND METHOD OF ION BEAM SOURCE FOR SEMICONDUCTOR ION IMPLANTATION 有权
标题翻译：用于半导体离子植入的离子束源的系统和方法
公开(公告)号：US20130270454A1
公开(公告)日：2013-10-17
申请号：US13443994
申请日：2012-04-11
申请人： Chih-Hong HWANG , Chun-Lin CHANG , Chi-Ming YANG , Chin-Hsiang LIN , Wen-Yu KU
发明人： Chih-Hong HWANG , Chun-Lin CHANG , Chi-Ming YANG , Chin-Hsiang LIN , Wen-Yu KU
IPC分类号： C23C14/48 , H01J27/02
CPC分类号： C23C14/48 , H01J27/08 , H01J37/08 , H01J2237/082 , H01J2237/31701
摘要： An apparatus comprises an ionization chamber for providing ions during a process of ion implantation, and an electron beam source device inside the ionization chamber. The electron beam source device comprises a field emission array having a plurality of emitters for generating electrons in vacuum under an electric field.
摘要翻译：一种装置包括用于在离子注入过程中提供离子的电离室和电离室内的电子束源装置。电子束源装置包括具有多个用于在电场下在真空中产生电子的发射器的场致发射阵列。

15. 发明申请

US20130023094A1 METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造集成电路装置的方法
公开(公告)号：US20130023094A1
公开(公告)日：2013-01-24
申请号：US13189108
申请日：2011-07-22
申请人： Ming-Hsi YEH , Hsien-Hsin LIN , Ying-Hsueh CHANG CHIEN , Yi-Fang PAI , Chi-Ming YANG , Chin-Hsiang LIN
发明人： Ming-Hsi YEH , Hsien-Hsin LIN , Ying-Hsueh CHANG CHIEN , Yi-Fang PAI , Chi-Ming YANG , Chin-Hsiang LIN
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823864 , Y10S438/976
摘要： A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.
摘要翻译：公开了一种用于制造集成器件的方法。当形成与由保护层未覆盖的另一个栅极结构相邻的外延（epi）特征时，在栅极结构上形成保护层。此后，在形成外延（epi）特征之后，去除保护层。所公开的方法提供了用于去除保护层而没有实质缺陷的改进方法。在一个实施方案中，改进的形成方法通过在氧化物基材料上提供保护剂，然后使用包含氢氟酸的化学品除去保护层来实现。

16. 发明申请

US20130285264A1 WAFER ASSEMBLY WITH CARRIER WAFER 有权
标题翻译：带载波的WAFER装配
公开(公告)号：US20130285264A1
公开(公告)日：2013-10-31
申请号：US13539243
申请日：2012-06-29
申请人： I-Hsiung HUANG , Heng-Hsin LIU , Heng-Jen LEE , Chin-Hsiang LIN
发明人： I-Hsiung HUANG , Heng-Hsin LIU , Heng-Jen LEE , Chin-Hsiang LIN
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/0201 , H01L21/6835 , H01L2221/6834 , H01L2221/68381
摘要： A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.
摘要翻译：晶片组件包括处理晶片和载体晶片。集成电路形成在处理晶片上。载体晶片结合到工艺晶片。载体晶片具有至少一个对准标记。

17. 发明申请

US20130171336A1 WAFER PROCESSING METHOD AND SYSTEM USING MULTI-ZONE CHUCK 有权
标题翻译：使用多区域切割的波浪加工方法和系统
公开(公告)号：US20130171336A1
公开(公告)日：2013-07-04
申请号：US13338885
申请日：2011-12-28
申请人： Nai-Han CHENG , Chi-Ming YANG , You-Hua CHOU , Kuo-Sheng CHUANG , Chin-Hsiang LIN
发明人： Nai-Han CHENG , Chi-Ming YANG , You-Hua CHOU , Kuo-Sheng CHUANG , Chin-Hsiang LIN
IPC分类号： C23C16/458 , B23Q7/00 , C23C14/50 , C23C16/52 , C23C14/54
CPC分类号： H01L21/68785 , C23C14/50 , C23C14/54 , C23C16/4582 , C23C16/52 , H01L21/67098 , H01L21/67288 , H01L21/6831 , Y10T29/49998
摘要： In a wafer processing method and a wafer processing system, a first property on a back side of a wafer is measured. The back side of the wafer is supported on a multi-zone chuck having a plurality of zones with controllable clamping forces. The wafer is secured to the multi-zone chuck by controlling the clamping forces in the corresponding zones in accordance with measured values of the first property in the zones.
摘要翻译：在晶片处理方法和晶片处理系统中，测量晶片背面的第一特性。晶片的背面被支撑在具有可控夹紧力的多个区域的多区域卡盘上。通过根据区域中的第一属性的测量值控制相应区域中的夹紧力将晶片固定到多区域卡盘。

18. 发明申请

US20110086504A1 METHODS FOR FORMING INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路的方法
公开(公告)号：US20110086504A1
公开(公告)日：2011-04-14
申请号：US12879371
申请日：2010-09-10
申请人： Kuo Bin HUANG , Hsin-Chien LU , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
发明人： Kuo Bin HUANG , Hsin-Chien LU , Ryan Chia-Jen CHEN , Chi-Ming YANG , Chyi Shyuan CHERN , Chin-Hsiang LIN
IPC分类号： H01L21/3205 , H01L21/302
CPC分类号： H01L21/28238 , H01L21/02071 , H01L21/823842 , H01L21/823857
摘要： A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.
摘要翻译：提供一种用于形成集成电路的方法。该方法包括在衬底上形成栅极电介质结构。形成与该栅电介质结构接触的含钛牺牲层。基本上除去了整个含钛牺牲层。

19. 发明申请

US20090011374A1 METHOD AND MATERIAL FOR FORMING HIGH ETCH RESISTANT DOUBLE EXPOSURE PATTERNS 有权
标题翻译：用于形成高耐蚀双重曝光图案的方法和材料
公开(公告)号：US20090011374A1
公开(公告)日：2009-01-08
申请号：US12205509
申请日：2008-09-05
申请人： Ching-Yu CHANG , Chin-Hsiang LIN
发明人： Ching-Yu CHANG , Chin-Hsiang LIN
IPC分类号： G03F7/20
CPC分类号： G03F7/40 , G03F7/405
摘要： The present invention includes a lithography method comprising forming a first patterned resist layer including at least one opening therein over a substrate. A protective layer is formed on the first patterned resist layer and the substrate whereby a reaction occurs at the interface between the first patterned resist layer and the protective layer to form a reaction layer over the first patterned resist layer. The non-reacted protective layer is then removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask.
摘要翻译：本发明包括光刻方法，包括在衬底上形成包括至少一个开口的第一图案化抗蚀剂层。在第一图案化抗蚀剂层和基板上形成保护层，由此在第一图案化抗蚀剂层和保护层之间的界面处发生反应，以在第一图案化抗蚀剂层上形成反应层。然后除去未反应的保护层。此后，在衬底上形成第二图案化抗蚀剂层，其中第二图案化抗蚀剂层的至少一部分设置在第一图案化抗蚀剂层的至少一个开口内。然后使用第一和第二图案化抗蚀剂层作为掩模蚀刻衬底。

20. 发明申请

US20070278424A1 METHOD AND APPARATUS TO IMPROVE LITHOGRAPHY THROUGHPUT 有权
标题翻译：改进算法的方法和装置
公开(公告)号：US20070278424A1
公开(公告)日：2007-12-06
申请号：US11421590
申请日：2006-06-01
申请人： Chin-Hsiang LIN , Jui-Chung PENG , Yung-Cheng CHEN , Shy-Jan LIN
发明人： Chin-Hsiang LIN , Jui-Chung PENG , Yung-Cheng CHEN , Shy-Jan LIN
IPC分类号： G03F7/20
CPC分类号： G03F7/70991 , G03F7/70466
摘要： The present disclosure provides a lithography apparatus with improved lithography throughput. The lithography apparatus includes a first lens system; a first substrate stage configured to receive a first radiation energy from the first lens system, and designed operable to move a substrate during an exposing process; a second lens system, having a higher resolution than that of the first lens system; and a second substrate stage approximate to the first substrate stage and configured to receive a second radiation energy from the second lens system, and designed operable to receive the substrate from the first substrate stage and move the substrate.
摘要翻译：本公开提供了具有改进的光刻产量的光刻设备。光刻设备包括第一透镜系统; 第一衬底台，被配置为从所述第一透镜系统接收第一辐射能量，并且被设计为可操作以在曝光过程期间移动衬底; 第二透镜系统，具有比第一透镜系统更高的分辨率; 以及第二衬底台，其近似于所述第一衬底台并且被配置为从所述第二透镜系统接收第二辐射能量，并且被设计为可操作以从所述第一衬底台接收所述衬底并移动所述衬底。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式