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11. 发明申请

US20130334575A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130334575A1
公开(公告)日：2013-12-19
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L27/10 , H01L21/768
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

12. 发明申请

US20130277852A1 Method for Creating a 3D Stacked Multichip Module 有权
标题翻译：创建3D堆叠多芯片模块的方法
公开(公告)号：US20130277852A1
公开(公告)日：2013-10-24
申请号：US13451411
申请日：2012-04-19
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L23/481 , H01L24/24 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/16146 , H01L2224/24011 , H01L2224/24146 , H01L2224/2919 , H01L2224/32145 , H01L2224/33181 , H01L2224/82031 , H01L2224/821 , H01L2224/83005 , H01L2224/83191 , H01L2224/8385 , H01L2224/9202 , H01L2225/06544 , H01L2225/06548 , H01L2225/06565 , H01L2924/00014 , H01L2224/82
摘要： A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
摘要翻译： 3D堆叠多芯片模块包括一堆W IC芯片。每个管芯具有图案化导体层，其包括与电导体的电接触区域，并且在一些示例中包括衬底上的器件电路。堆叠管芯的电导体对齐。电连接器延伸到堆叠中以接触电导体上的着陆焊盘，以产生3D堆叠多芯片模块。电连接器可以穿过电接触区域中的垂直通孔。着陆垫可以布置成阶梯式的台阶。堆叠的多芯片模块可以使用一组N个蚀刻掩模制成，其中2N-1小于W且2N大于或等于W，其中蚀刻掩模交替地覆盖并暴露每个掩模的2n-1个着陆焊盘n = 1，2。。。 N.

13. 发明申请

US20130214340A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20130214340A1
公开(公告)日：2013-08-22
申请号：US13401634
申请日：2012-02-21
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/68 , H01L21/283
CPC分类号： H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L29/7881 , H01L29/792
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基板，第一堆叠结构和第一导电层。第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

14. 发明授权

US08503213B2 Memory architecture of 3D array with alternating memory string orientation and string select structures 有权
标题翻译：具有交替的内存字符串方向和字符串选择结构的3D阵列的内存架构
公开(公告)号：US08503213B2
公开(公告)日：2013-08-06
申请号：US13078311
申请日：2011-04-01
申请人： Shih-Hung Chen , Hang-Ting Lue
发明人： Shih-Hung Chen , Hang-Ting Lue
IPC分类号： G11C5/06
CPC分类号： H01L27/11578 , G11C13/0002 , G11C16/0483 , G11C17/16 , G11C2213/71 , G11C2213/75 , H01L27/11573
摘要： A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.
摘要翻译： 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。二极管与字符串的公共源选择端的字符串选择连接到位线。导电材料条具有在脊形叠层的侧面上的侧表面。可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。

15. 发明申请

US20120182806A1 Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures 有权
标题翻译：具有交替内存字符串方向和字符串选择结构的3D阵列的内存架构
公开(公告)号：US20120182806A1
公开(公告)日：2012-07-19
申请号：US13078311
申请日：2011-04-01
申请人： Shih-Hung Chen , Hang-Ting Lue
发明人： Shih-Hung Chen , Hang-Ting Lue
IPC分类号： G11C16/04
CPC分类号： H01L27/11578 , G11C13/0002 , G11C16/0483 , G11C17/16 , G11C2213/71 , G11C2213/75 , H01L27/11573
摘要： A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.
摘要翻译： 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。二极管与字符串的公共源选择端的字符串选择连接到位线。导电材料条具有在脊形叠层的侧面上的侧表面。可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。

16. 发明授权

US08168538B2 Buried silicide structure and method for making 有权
标题翻译：埋地硅化物结构及其制造方法
公开(公告)号：US08168538B2
公开(公告)日：2012-05-01
申请号：US12472158
申请日：2009-05-26
申请人： Shih-Hung Chen , Tian-Jue Hong
发明人： Shih-Hung Chen , Tian-Jue Hong
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L27/101 , H01L21/743 , H01L21/8221 , H01L27/0688 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675 , H01L45/1683
摘要： Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.
摘要翻译：本文描述了用于制造掩埋硅化物线的方法，以及高密度堆叠存储器结构。如本文所述的用于制造集成电路的方法包括形成包括硅的半导体本体。在半导体本体中形成多个沟槽以限定在相邻沟槽之间包括硅的半导体线，半导体线具有侧壁。在沟槽内沉积硅化物前体以接触半导体管线的侧壁，并且去除硅化物前体的一部分以暴露侧壁的上部，并沿侧壁留下剩余的硅化物前体条。然后通过引起硅化物条与半导体线的硅的反应形成硅化物导体。

17. 发明申请

US20120080716A1 INITIAL-ON SCR DEVICE FOR ON-CHIP ESD PROTECTION 审中-公开
标题翻译：用于片上ESD保护的初始化SCR器件
公开(公告)号：US20120080716A1
公开(公告)日：2012-04-05
申请号：US13327171
申请日：2011-12-15
申请人： Ming-Dou Ker , Shih-Hung Chen , Kun-Hsien Lin
发明人： Ming-Dou Ker , Shih-Hung Chen , Kun-Hsien Lin
IPC分类号： H01L29/772
CPC分类号： H01L23/62 , H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.
摘要翻译：一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接到PMOS晶体管的第二扩散区域。

18. 发明授权

US08097871B2 Low operational current phase change memory structures 有权
标题翻译：低工作电流相变存储器结构
公开(公告)号：US08097871B2
公开(公告)日：2012-01-17
申请号：US12433573
申请日：2009-04-30
申请人： Shih-Hung Chen , Yi-Chou Chen
发明人： Shih-Hung Chen , Yi-Chou Chen
IPC分类号： H01L47/00
CPC分类号： H01L45/122 , H01L27/2436 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1616 , H01L45/1641 , H01L45/1675 , Y10S977/943
摘要： Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.
摘要翻译：与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。结果，相对于传统的蘑菇型存储单元，每单位电流值在横向边缘内产生的热量增加。因此，引起相变所需的电流量减少。

19. 发明授权

US07804083B2 Phase change memory cell including a thermal protect bottom electrode and manufacturing methods 有权
标题翻译：相变存储单元包括热保护底电极和制造方法
公开(公告)号：US07804083B2
公开(公告)日：2010-09-28
申请号：US11940164
申请日：2007-11-14
申请人： Shih-Hung Chen
发明人： Shih-Hung Chen
IPC分类号： H01L47/00 , H01L29/04 , H01L31/036
CPC分类号： H01L45/143 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a bottom electrode, a thermal protect structure on the bottom electrode, and a multi-layer stack on the thermal protect structure. The thermal protect structure comprises a layer of thermal protect material, the thermal protect material having a thermal conductivity less than that of the bottom electrode material.
摘要翻译：存储器件与制造方法一起被描述。如本文所述的存储器件的实施例包括底部电极，底部电极上的热保护结构以及热保护结构上的多层堆叠。热保护结构包括一层热保护材料，该热保护材料的热导率小于底部电极材料的热导率。

20. 发明授权

US07786460B2 Phase change memory device and manufacturing method 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07786460B2
公开(公告)日：2010-08-31
申请号：US11621390
申请日：2007-01-09
申请人： Hsiang Lan Lung , Shih-Hung Chen
发明人： Hsiang Lan Lung , Shih-Hung Chen
IPC分类号： H01L21/06 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1691
摘要： A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.
摘要翻译：相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于彼此之间并将电极的相对接触元件彼此电耦合的相变元件。相变元件具有宽度，长度和厚度。长度，厚度和宽度小于用于形成相变存储器单元的工艺的最小光刻特征尺寸。可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变元件的长度和宽度都小于最小光刻特征尺寸。

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