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11. 发明授权

US07067869B2 Adjustable 3D capacitor 有权
公开(公告)号：US07067869B2
公开(公告)日：2006-06-27
申请号：US10755495
申请日：2004-01-12
申请人： Wei Hua Cheng , Daniel Yen , Chit Hwei Ng , Marvin Liao
发明人： Wei Hua Cheng , Daniel Yen , Chit Hwei Ng , Marvin Liao
IPC分类号： H01L29/92
CPC分类号： H01G4/33 , H01G4/005 , H01G4/228 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

12. 发明授权

US06689643B2 Adjustable 3D capacitor 失效
公开(公告)号：US06689643B2
公开(公告)日：2004-02-10
申请号：US10132337
申请日：2002-04-25
申请人： Wei Hua Cheng , Daniel Yen , Chit Hwei Ng , Marvin Liao
发明人： Wei Hua Cheng , Daniel Yen , Chit Hwei Ng , Marvin Liao
IPC分类号： H01L2182
CPC分类号： H01G4/33 , H01G4/005 , H01G4/228 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

13. 发明授权

US06686279B2 Method for reducing gouging during via formation 失效
标题翻译：通孔形成时减少气刨的方法
公开(公告)号：US06686279B2
公开(公告)日：2004-02-03
申请号：US10114680
申请日：2002-04-01
申请人： Daniel Yen , Wei Hua Cheng , Yakub Aliyu , Lee Yuan Ping
发明人： Daniel Yen , Wei Hua Cheng , Yakub Aliyu , Lee Yuan Ping
IPC分类号： H01L2144
CPC分类号： H01L21/76831 , H01L21/76802
摘要： A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target. In this embodiment, liner material residing in the region where the opening is unlanded prevents further gouging of the substrate proximate to the target.
摘要翻译：一种用于在通孔形成期间减少气刨的方法和装置。在一个实施例中，本发明包括一种方法，该方法包括在基底中形成开口。开口形成为延伸到基板中并终止于期望形成电连接的目标的至少一部分上。在形成开口之后，本实施例用衬里材料排列开口。在该实施例中，衬垫材料适于至少部分地填充未着陆在靶上的开口的一部分。本实施例的衬垫材料防止了通常由开口至少部分地不在目标上引起的基板的进一步蚀刻。接下来，本实施例使衬里材料进行蚀刻工艺，使得衬里材料基本上从开口落在靶上的靶的区域中去除。在这个实施例中，位于开口未被覆盖的区域中的衬垫材料防止了靠近靶的衬底进一步的刨削。

14. 发明授权

US06630380B1 Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) 失效
标题翻译：制造用于动态随机存取存储器（DRAM）和铁电随机存取存储器（FERAM）的三维金属 - 绝缘体 - 金属电容器的方法
公开(公告)号：US06630380B1
公开(公告)日：2003-10-07
申请号：US10261303
申请日：2002-09-30
申请人： Wei-Hua Cheng , Daniel Yen , Kunihiko Takahashi , Ming Lei , Thomas Joy
发明人： Wei-Hua Cheng , Daniel Yen , Kunihiko Takahashi , Ming Lei , Thomas Joy
IPC分类号： H01L218242
CPC分类号： H01L21/76895 , H01L27/10855 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant or ferroelectric interelectrode films compatible with the dual-damascene process is achieved. The method of integrating the MIM with a dual-damascene process is to form a planar a first insulating layer and to deposit an etch-stop layer and a second insulating layer. Capacitor node contact openings are etched to the substrate and first recesses are etched to the etch-stop layer. The contact openings and first recesses are filled with a conducting layer using a dual-damascene process. Second recesses are formed in the second insulating layer around the capacitor node contacts. A conformal first metal layer, an interelectrode dielectric layer, and a second metal layer are deposited, and are patterned at the same time to form the capacitors over the node contacts. The second recesses increase the capacitor area while the simultaneous patterning of the metal layers results in fewer processing steps.
摘要翻译：实现了具有与双镶嵌工艺兼容的高介电常数或铁电电极间绝缘体的金属绝缘体金属（MIM）电容器的方法。将MIM与双镶嵌工艺集成的方法是形成平面的第一绝缘层并沉积蚀刻停止层和第二绝缘层。将电容器节点接触开口蚀刻到衬底上，并将第一凹槽蚀刻到蚀刻停止层。接触开口和第一凹槽使用双镶嵌工艺填充导电层。第二凹陷形成在电容器节点触点周围的第二绝缘层中。沉积保形第一金属层，电极间电介质层和第二金属层，并且同时形成图案以在节点触点上形成电容器。第二凹槽增加了电容器面积，而金属层的同时构图导致较少的加工步骤。

15. 发明授权

US06576526B2 Darc layer for MIM process integration 有权
标题翻译：用于MIM工艺集成的Darc层
公开(公告)号：US06576526B2
公开(公告)日：2003-06-10
申请号：US09900398
申请日：2001-07-09
申请人： Shao Kai , Wu-Guan Ping , Chen Liang , Cheng-Wei Hua , Sanford Chu , Daniel Yen
发明人： Shao Kai , Wu-Guan Ping , Chen Liang , Cheng-Wei Hua , Sanford Chu , Daniel Yen
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/32136
摘要： A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.
摘要翻译：为MIM电容器的创建提供了新的处理顺序。该过程开始于沉积第一层金属。接下来是沉积列表，薄层金属，一层绝缘层，第二层金属和一层抗反射涂层。然后进行蚀刻以形成MIM电容器的第二电极（使用蚀刻停止层来停止该蚀刻），MIM间隔物形成在MIM电容器的第二电极的侧壁上（也使用蚀刻停止层停止这个蚀刻）。 MIM电容器的电介质和第一电极通过蚀刻穿过第二绝缘层和第一金属层而形成。接下来是常规处理以产生与MIM电容器的接触点。

16. 发明授权

US06803305B2 Method for forming a via in a damascene process 有权
标题翻译：在镶嵌工艺中形成通孔的方法
公开(公告)号：US06803305B2
公开(公告)日：2004-10-12
申请号：US10120755
申请日：2002-04-10
申请人： Daniel Yen , Wei Hua Cheng , Yakub Aliyu , Ding Yi
发明人： Daniel Yen , Wei Hua Cheng , Yakub Aliyu , Ding Yi
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76807 , H01L2221/1063
摘要： A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.
摘要翻译：一种在镶嵌工艺中形成通孔的方法。在一个实施例中，本方法包括将材料沉积到使用镶嵌工艺形成的通孔中。更具体地说，在一个实施方案中，由基本上保形材料组成的材料，其相对于其中形成通孔的衬底具有蚀刻选择性。此外，在本实施例中，材料沿通孔的侧壁和基底沉积。接下来，本实施例蚀刻材料，使得通孔形成具有有利于其上覆盖材料的粘附的轮廓。在本实施例中，对基板进行蚀刻，而不会基本上蚀刻形成通孔的基板。在这样做时，本实施例在镶嵌工艺中形成通孔，其允许形成基本上没有空隙的金属化互连。

17. 发明授权

US06713335B2 Method of self-aligning a damascene gate structure to isolation regions 失效
标题翻译：将镶嵌栅极结构自对准到隔离区域的方法
公开(公告)号：US06713335B2
公开(公告)日：2004-03-30
申请号：US10225805
申请日：2002-08-22
申请人： Daniel Yen , Ching-Thiam Chung , Wei Hua Cheng , Chester Nieh , Tong Boon Lee
发明人： Daniel Yen , Ching-Thiam Chung , Wei Hua Cheng , Chester Nieh , Tong Boon Lee
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28097 , H01L21/28167 , H01L21/76229 , H01L21/823878 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/66492 , H01L29/66545 , H01L29/66553 , H01L29/6659
摘要： A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.
摘要翻译：已经开发了制造CMOS器件的方法，其中导电栅结构被限定为与浅沟槽隔离（STI）区域自对准，而不使用光刻工艺。该工艺的特征是在未被虚拟栅极结构覆盖的半导体衬底的区域中或通过位于虚拟栅极结构的侧面上的氧化硅间隔区的浅沟槽开口的定义。用氧化硅填充浅沟槽开口和去除虚拟栅极结构导致STI区域由覆盖的氧化硅形状的填充的浅沟槽开口和覆盖的氧化硅形状的侧面上的氧化硅侧壁间隔件组成。在STI区域的侧面上形成氮化硅间隔物，随后沉积高k栅极绝缘体层和导电栅极结构，导电栅极结构与STI区域自对准。

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