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11. 发明授权

US08420470B2 Method of fabricating a semiconductor device using compressive material with a replacement gate technique 有权
标题翻译：使用替代栅极技术制造使用压缩材料的半导体器件的方法
公开(公告)号：US08420470B2
公开(公告)日：2013-04-16
申请号：US12869341
申请日：2010-08-26
申请人： Kisik Choi
发明人： Kisik Choi
IPC分类号： H01L21/338 , H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/76801 , H01L21/76829 , H01L29/7843
摘要： The disclosed method of fabricating a semiconductor device structure forms a dummy gate structure on a substrate, deposits a dielectric material overlying the dummy gate structure in a manner that forms angled sidewalls of the deposited dielectric material outboard the spacers, and conformally deposits a compressive material overlying the deposited dielectric material such that the deposited compressive material forms angled peaks overlying the dummy gate structure. The method continues by forming an upper dielectric layer overlying the deposited compressive material, planarizing the resulting device structure, and exposing the temporary gate element of the dummy gate structure. Thereafter, the temporary gate element is removed, while leaving sections of the deposited compressive material outboard the spacers, and the gate recess is filled with a gate electrode material. The compressive material pulls the upper ends of the spacers apart to facilitate filling the gate recess.
摘要翻译：所公开的制造半导体器件结构的方法在衬底上形成虚拟栅极结构，以覆盖虚拟栅极结构的方式沉积介电材料，其方式是在隔离物外侧形成沉积的介电材料的成角度的侧壁，并且共形地沉积覆盖的压缩材料沉积的介电材料使得沉积的压缩材料形成覆盖在虚拟栅极结构上的倾斜峰值。该方法通过形成覆盖沉积的压缩材料的上介电层，平坦化所得到的器件结构，以及暴露伪栅极结构的临时栅极元件来继续。此后，移除临时栅极元件，同时将沉积的压缩材料的部分留在隔板上，并且栅极凹槽填充有栅电极材料。压缩材料将间隔物的上端拉开以便于填充浇口凹槽。

12. 发明授权

US09218975B2 Methods of forming a replacement gate structure having a gate electrode comprised of a deposited intermetallic compound material 有权
标题翻译：形成具有由沉积的金属间化合物材料构成的栅电极的替代栅结构的方法
公开(公告)号：US09218975B2
公开(公告)日：2015-12-22
申请号：US13588517
申请日：2012-08-17
申请人： Kisik Choi , Mark V. Raymond
发明人： Kisik Choi , Mark V. Raymond
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28088 , H01L21/28097 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： Disclosed herein are various methods of forming a replacement gate structure with a gate electrode comprised of a deposited intermetallic compound material. In one example, the method includes removing at least a sacrificial gate electrode structure to define a gate cavity, forming a gate insulation layer in the gate cavity, performing a deposition process to deposit an intermetallic compound material in the gate cavity above the gate insulation layer, and performing at least one process operation to remove portions of intermetallic compound material positioned outside of the gate cavity.
摘要翻译：本文公开了通过由沉积的金属间化合物材料构成的栅电极形成替代栅极结构的各种方法。在一个示例中，该方法包括去除至少牺牲栅极电极结构以限定栅极腔，在栅极腔中形成栅极绝缘层，执行沉积工艺以在栅极绝缘层上方的栅极腔中沉积金属间化合物材料，并且执行至少一个处理操作以去除位于栅腔外部的金属间化合物材料的部分。

13. 发明授权

US08853069B2 Field effect transistor and method of fabrication 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US08853069B2
公开(公告)日：2014-10-07
申请号：US13607954
申请日：2012-09-10
申请人： Hoon Kim , Kisik Choi , Chanro Park
发明人： Hoon Kim , Kisik Choi , Chanro Park
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/28 , H01L29/49 , H01L29/78 , H01L29/66 , H01L29/51
CPC分类号： H01L29/4966 , H01L21/28008 , H01L21/28088 , H01L21/28194 , H01L29/4236 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.
摘要翻译：公开了一种改进的场效应晶体管及其制造方法。在栅腔的基底和侧壁中形成阻挡层堆叠。阻挡层堆叠具有第一金属层和第二金属层。栅极电极金属沉积在空腔中。阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

14. 发明申请

US20130292744A1 INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE 有权
标题翻译：集成电路及其替代盖结构的方法
公开(公告)号：US20130292744A1
公开(公告)日：2013-11-07
申请号：US13462619
申请日：2012-05-02
申请人： Hoon Kim , Kisik Choi
发明人： Hoon Kim , Kisik Choi
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L29/66545 , H01L29/66553
摘要： An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 Å in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.
摘要翻译：集成电路包括第一替换栅极结构。第一替代栅极结构包括厚度小于20μm的第一阻挡材料层和p型功函数材料层。替代栅极结构的宽度小于约50nm。

15. 发明授权

US08564066B2 Interface-free metal gate stack 有权
标题翻译：无接口的金属栅极堆叠
公开(公告)号：US08564066B2
公开(公告)日：2013-10-22
申请号：US12818828
申请日：2010-06-18
申请人： Takashi Ando , Kisik Choi , Matthew W. Copel , Richard A. Haight
发明人： Takashi Ando , Kisik Choi , Matthew W. Copel , Richard A. Haight
IPC分类号： H01L21/70
CPC分类号： H01L21/823828 , H01L21/02164 , H01L21/28 , H01L21/28088 , H01L21/28238 , H01L21/823842 , H01L27/092 , H01L29/517
摘要： A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
摘要翻译：制造晶体管的栅叠层的方法包括在半导体层上形成高介电常数层。在高介电常数层上形成金属层。在金属层上形成含硅层。在含硅层形成期间偶然形成氧化层，并且位于含硅层下面的金属层上。除去含硅层。在除去含硅层之后，去除位于金属层上的氧化层。

16. 发明申请

US20130154019A1 LOW THRESHOLD VOLTAGE CMOS DEVICE 有权
标题翻译：低电压电压CMOS器件
公开(公告)号：US20130154019A1
公开(公告)日：2013-06-20
申请号：US13327870
申请日：2011-12-16
申请人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
摘要翻译：一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。还公开了制造半导体器件的方法，其包括栅极最后工艺。

17. 发明授权

US08048791B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US08048791B2
公开(公告)日：2011-11-01
申请号：US12390907
申请日：2009-02-23
申请人： Michael Hargrove , Richard J. Carter , Ying H Tsang , George Kluth , Kisik Choi
发明人： Michael Hargrove , Richard J. Carter , Ying H Tsang , George Kluth , Kisik Choi
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66651 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L29/1054 , H01L29/513 , H01L29/517
摘要： Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.
摘要翻译：提供了形成包括半导体衬底的半导体器件的方法。根据示例性实施例，一种方法包括形成覆盖在半导体衬底上的沟道层，形成通道封盖层，其具有覆盖沟道层的第一表面，氧化沟道封盖层的第一表面，以及沉积高k电介质覆盖通道封盖层的层。

18. 发明申请

US20100193896A1 METHOD FOR NITRIDATION OF SHALLOW TRENCH ISOLATION STRUCTURE TO PREVENT OXYGEN ABSORPTION 审中-公开
标题翻译：用于减少高温分离结构以防止氧气吸收的方法
公开(公告)号：US20100193896A1
公开(公告)日：2010-08-05
申请号：US12363822
申请日：2009-02-02
申请人： Kisik Choi , Changhwan Choi , Vijay Narayanan
发明人： Kisik Choi , Changhwan Choi , Vijay Narayanan
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： A method for forming an isolation structure includes forming a trench in a semiconductor layer. At least a portion of the trench is filled with a dielectric material including oxygen. A region comprising nitrogen is formed in at least an upper portion of the dielectric material.
摘要翻译：形成隔离结构的方法包括在半导体层中形成沟槽。沟槽的至少一部分填充有包括氧的电介质材料。包含氮的区域形成在电介质材料的至少上部。

19. 发明授权

US08941184B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US08941184B2
公开(公告)日：2015-01-27
申请号：US13327870
申请日：2011-12-16
申请人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
摘要翻译：一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。还公开了制造半导体器件的方法，其包括栅极最后工艺。

20. 发明授权

US08592296B2 Gate-last fabrication of quarter-gap MGHK FET 有权
标题翻译：最后制造四分之一MGHK FET
公开(公告)号：US08592296B2
公开(公告)日：2013-11-26
申请号：US12816605
申请日：2010-06-16
申请人： Takashi Ando , Kisik Choi , Vijay Narayanan , Tenko Yamashita , Junli Wang
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan , Tenko Yamashita , Junli Wang
IPC分类号： H01L21/3205
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.
摘要翻译：通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

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