会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 13. 发明授权
    • Method of fabricating chips and an associated support
    • 制造芯片和相关支持的方法
    • US07544586B2
    • 2009-06-09
    • US11136252
    • 2005-05-23
    • Bruno GhyselenOlivier Rayssac
    • Bruno GhyselenOlivier Rayssac
    • H01L21/00
    • H01L21/78H01L2924/0002H01L2924/00
    • A method of fabricating a plurality of chips, with each chip including at least one circuit. This method includes the successive steps of creating chips on a layer of semiconductor material that is integral with a substrate; forming a weakening pattern corresponding to a predetermined cutting pattern on a support; transferring the chip-containing layer from the substrate to the support; and forming individual chips by cutting the chip-containing layer in accordance with the predetermined cutting pattern. Also, an assembly for fabricating a plurality of chips, each chip including at least one circuit provided on a layer of semiconductor material that is carried by a support that includes a weakening pattern corresponding to a predetermined cutting pattern for forming individual chips, with the support being obtained by assembling a plurality of individual tiles with boundaries between the individual tiles corresponding to the weakening pattern. The tiles may be assembled by disposing a binder between the individual tiles, with the binder ensuring temporary bonding of the tiles.
    • 一种制造多个芯片的方法,每个芯片包括至少一个电路。 该方法包括在与衬底成一体的半导体材料层上产生芯片的连续步骤; 在支撑件上形成对应于预定切割图案的削弱图案; 将含芯片的层从基底转移到载体上; 以及通过根据预定的切割图案切割含芯片层而形成单独的芯片。 另外,用于制造多个芯片的组件,每个芯片包括至少一个电路,该至少一个电路设置在由支撑体承载的半导体材料层上,所述支撑件包括对应于用于形成单独芯片的预定切割图案的弱化图案,支撑件 通过组合具有对应于弱化图案的各个瓦片之间的边界的多个单独的瓦片来获得。 可以通过在各个瓦片之间设置粘合剂来组装瓦片,粘合剂确保瓦片的临时粘合。