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11. 发明授权

US07714358B2 Semiconductor structure and method of forming the structure 失效
标题翻译：半导体结构及其形成方法
公开(公告)号：US07714358B2
公开(公告)日：2010-05-11
申请号：US11672599
申请日：2007-02-08
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

12. 发明申请

US20100112766A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：半导体结构和形成结构的方法
公开(公告)号：US20100112766A1
公开(公告)日：2010-05-06
申请号：US12685027
申请日：2010-01-11
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

13. 发明授权

US07932144B2 Semiconductor structure and method of forming the structure 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US07932144B2
公开(公告)日：2011-04-26
申请号：US12685027
申请日：2010-01-11
申请人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
发明人： Yaocheng Liu , Shreesh Narasimha , Katsunori Onishi , Kern Rim
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , H01L21/26506 , H01L21/26513 , H01L21/28247 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.
摘要翻译：公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。因此，可以更深地形成碳注入区域。完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

14. 发明申请

US20050285159A1 Compressive SiGe <110> growth and structure of MOSFET devices 有权
标题翻译：压电SiGe <110> MOSFET器件的增长和结构
公开(公告)号：US20050285159A1
公开(公告)日：2005-12-29
申请号：US10875727
申请日：2004-06-24
申请人： Kevin Chan , Kathryn Guarini , Meikel Ieong , Kern Rim , Min Yang
发明人： Kevin Chan , Kathryn Guarini , Meikel Ieong , Kern Rim , Min Yang
IPC分类号： H01L21/20 , H01L21/205 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/823807 , H01L29/1054
摘要： A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HCl acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.
摘要翻译：描述了用于导电载体的结构和形成方法，其结合了具有在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此形成PS形态层正在紧张。描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃来形成拟态或外延层的步骤，并引入含Si气体和含Ge的气体。描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底以获得不含杂质且RMS小于0.1nm的衬底表面。

15. 发明授权

US06451702B1 Methods for forming lateral trench optical detectors 失效
标题翻译：形成横向沟槽光学检测器的方法
公开(公告)号：US06451702B1
公开(公告)日：2002-09-17
申请号：US09784963
申请日：2001-02-16
申请人： Min Yang , Kern Rim
发明人： Min Yang , Kern Rim
IPC分类号： H01L21302
CPC分类号： H01L27/1446 , H01L31/035281 , H01L31/103 , H01L31/105 , Y02E10/50
摘要： A method for forming an optical detector device on a semiconductor substrate. The method includes forming a first set and a second set of trenches in the substrate, wherein trenches of the first set are alternately disposed with respect to trenches of the second set, filling the trenches with a sacrificial material, and etching the sacrificial material from the first set of trenches. The method further includes filling the first set of trenches with a doped material of a first conductivity, etching the sacrificial material from a second set of trenches, filling the second set of trenches with a doped material of a second conductivity, forming a first junction layer by driving dopants from the doped material in each of the first set of trenches and forming a second junction layer by driving dopants from the doped material in each of the second set of trenches, and providing separate wiring connections to the first set of trenches and the second set of trenches. The first and second set of trenches are formed simultaneously.
摘要翻译：一种在半导体衬底上形成光检测器件的方法。该方法包括在衬底中形成第一组和第二组沟槽，其中第一组的沟槽相对于第二组的沟槽交替地设置，用牺牲材料填充沟槽，并且从牺牲材料中蚀刻牺牲材料第一套壕沟。该方法还包括用第一导电性的掺杂材料填充第一组沟槽，从第二组沟槽蚀刻牺牲材料，用第二导电体的掺杂材料填充第二组沟槽，形成第一结层通过从第一组沟槽中的每一个中的掺杂材料驱动掺杂剂并且通过从第二组沟槽中的每一个中的掺杂材料驱动掺杂物并且提供到第一组沟槽的分离的布线连接而形成第二结层，并且第二套壕沟。第一和第二组沟槽同时形成。

16. 发明授权

US06667528B2 Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same 有权
标题翻译：具有反射镜和背面接触的绝缘体上半导体侧面p-i-n光电探测器及其形成方法
公开(公告)号：US06667528B2
公开(公告)日：2003-12-23
申请号：US10033902
申请日：2002-01-03
申请人： Guy Moshe Cohen , Kern Rim , Dennis L. Rogers , Jeremy Daniel Schaub , Min Yang
发明人： Guy Moshe Cohen , Kern Rim , Dennis L. Rogers , Jeremy Daniel Schaub , Min Yang
IPC分类号： H01L31058
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/03921 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.
摘要翻译：光电检测器（及其制造方法）包括半导体衬底，形成在衬底上的埋入绝缘体，形成在埋层绝缘体上的掩埋反射镜，形成在导体上的绝缘体上半导体层（SOI）层，形成在绝缘体上半导体层中的p型和p型掺杂指，以及与p型掺杂指和n型掺杂指之一的背面接触。

17. 发明申请

US20120149159A1 STRUCTURE AND METHOD FOR MOBILITY ENHANCED MOSFETS WITH UNALLOYED SILICIDE 有权
公开(公告)号：US20120149159A1
公开(公告)日：2012-06-14
申请号：US13397865
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

18. 发明授权

US07888264B2 MOSFET structure with multiple self-aligned silicide contacts 有权
标题翻译：具有多个自对准硅化物触点的MOSFET结构
公开(公告)号：US07888264B2
公开(公告)日：2011-02-15
申请号：US12814942
申请日：2010-06-14
申请人： Kevin K. Chan , Christian Lavoie , Kern Rim
发明人： Kevin K. Chan , Christian Lavoie , Kern Rim
IPC分类号： H01L21/44
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

19. 发明授权

US07682915B2 Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance 有权
标题翻译：具有非常低温选择性外延的预外延一次性间隔物集成方案，以提高器件性能
公开(公告)号：US07682915B2
公开(公告)日：2010-03-23
申请号：US12100644
申请日：2008-04-10
申请人： Huajie Chen , Judson R. Holt , Kern Rim , Dominic J. Schepis
发明人： Huajie Chen , Judson R. Holt , Kern Rim , Dominic J. Schepis
IPC分类号： H01L21/336
CPC分类号： H01L21/823864 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More specifically, one method begins by forming a first gate and a second gate on a substrate. Next, an oxide layer is formed on the first and second gates; and, a nitride layer is formed on the oxide layer. Portions of the nitride layer proximate the first gate, portions of the oxide layer proximate the first gate, and portions of the substrate proximate the first gate are removed so as to form source and drain recesses proximate the first gate. Following this, the method removes remaining portions of the nitride layer, including exposing remaining portions of the oxide layer. The removal of the remaining portions of the nitride layer only exposes the remaining portions of the oxide layer and the source and drain recesses.
摘要翻译：本发明的实施例提供了一种用于具有非常低的温度选择性外延的预外延一次性间隔物集成方案的方法等，以增强器件性能。更具体地，一种方法是通过在衬底上形成第一栅极和第二栅极开始的。接下来，在第一和第二栅极上形成氧化物层; 并且在氧化物层上形成氮化物层。接近第一栅极的氮化物层的部分，靠近第一栅极的氧化物层的部分以及靠近第一栅极的衬底的部分被去除，以便形成靠近第一栅极的源极和漏极。接下来，该方法去除氮化物层的剩余部分，包括暴露氧化物层的剩余部分。去除氮化物层的剩余部分仅暴露氧化物层和源极和漏极凹槽的剩余部分。

20. 发明授权

US07605077B2 Dual metal integration scheme based on full silicidation of the gate electrode 失效
标题翻译：基于栅电极完全硅化的双金属集成方案
公开(公告)号：US07605077B2
公开(公告)日：2009-10-20
申请号：US11308486
申请日：2006-03-29
申请人： William K. Henson , Kern Rim , Jack A. Mandelman
发明人： William K. Henson , Kern Rim , Jack A. Mandelman
IPC分类号： H01L21/40 , H01L29/45
CPC分类号： H01L21/823443 , H01L21/82345 , H01L21/823835 , H01L21/823842
摘要： An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.
摘要翻译：提供了与源极/漏极区域同时实现nFET和pFET栅电极的全硅化（FUSI）的集成方案。栅电极的FUSI消除了多晶硅栅电极观察到的栅耗尽问题。此外，本发明的集成方案刚好在硅化之前产生栅电极的不同硅厚度。本发明的该特征允许制造具有针对特定器件区域定制的带边缘功能函数的nFET和pFET。

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