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11. 发明授权

US5805513A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
公开(公告)号：US5805513A
公开(公告)日：1998-09-08
申请号：US432867
申请日：1995-05-02
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takekuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50 , G11C7/00
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

12. 发明授权

US5726994A Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof 失效
标题翻译：地址多路复用半导体存储器件，用于使得能够测试整个电路或仅对其部分部件进行测试
公开(公告)号：US5726994A
公开(公告)日：1998-03-10
申请号：US608616
申请日：1996-02-29
申请人： Hiromi Matsuura , Masaya Muranaka , Yasunori Orito
发明人： Hiromi Matsuura , Masaya Muranaka , Yasunori Orito
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/18 , G11C29/34 , H01L21/66 , G11C7/00
CPC分类号： G11C29/18
摘要： A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.
摘要翻译：存储器阵列在逻辑上和/或物理上被划分成多个块，以允许单个块进行测试。当提供多个列地址选通信号并且通过多个位对与列地址选通信号相对应的存储器阵列进行存储器访问时，通过使用列地址选通信号独立地对每个存储器阵列进行测试。

13. 发明授权

US5301142A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5301142A
公开(公告)日：1994-04-05
申请号：US895598
申请日：1992-06-08
申请人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
发明人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/10
摘要： Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.
摘要翻译：在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。指定对应的存储器垫的位线选择性地连接到第一公共数据线。还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。指定的子IO线选择性地连接到第二公共数据线。此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。这些主放大器按照所涉及的工作模式正确使用。由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

14. 发明授权

US07588507B2 Thin autotensioner 失效
公开(公告)号：US07588507B2
公开(公告)日：2009-09-15
申请号：US09961365
申请日：2001-09-25
申请人： Kazumasa Ayukawa , Hiromi Matsuura
发明人： Kazumasa Ayukawa , Hiromi Matsuura
IPC分类号： F16H7/08 , F16H55/32
CPC分类号： F16H7/1218 , F16H2007/081 , F16H2007/084 , Y10T29/49615
摘要： An autotensioner comprises a torsion coil spring interposed between a base and a rocking arm, and a tubular bushing provided between an inside surface of the base and an outside surface of the rocking arm. The torsion coil spring pushes and biases the rocking arm toward the bushing, and brings the pushing direction substantially in coincidence with the axial load direction of the force, acting on a stepped bolt supporting the rocking arm, from a belt. When the belt tension becomes high, the arm axial center displaces slightly from the base axial center, an extremely large first damping force acts on the rocking arm. When the belt tension becomes low, the smaller second damping force acts on the rocking arm.

15. 发明授权

US06497632B2 Autotensioner 有权
标题翻译：自动张紧器
公开(公告)号：US06497632B2
公开(公告)日：2002-12-24
申请号：US09725073
申请日：2000-11-29
申请人： Kazumasa Ayukawa , Hiromi Matsuura
发明人： Kazumasa Ayukawa , Hiromi Matsuura
IPC分类号： F16H708
CPC分类号： F16H7/1218 , F16H2007/081
摘要： An autotensioner having a support shaft affixed to a base, and a cup of a swing member provided swingably about the support shaft. The cup opens to the base and houses inside it a torsion coil spring for biasing the pulley in the direction tensioning the belt. A damping member braking the swing member is fixed to the base. A ring-shaped spring brings it into close contact with the inner circumferential surface close to the opening of the cup. The damping member frictionally slides with the inner circumferential surface at the time of swing of the swing member and supports the swing member in the radial direction at the base side from the bearing supporting the support shaft.
摘要翻译：具有固定在基座上的支撑轴的自动张紧器以及围绕支承轴摆动地设置的摆动件的杯子。杯子通向底座并在其内部容纳扭转螺旋弹簧，用于沿着张紧皮带的方向偏置滑轮。制动摆动构件的阻尼构件固定在基座上。环形弹簧使其与靠近杯的开口的内周表面紧密接触。阻尼构件在摆动构件的摆动时与内周面摩擦滑动，并且在支撑支承轴的轴承的基部侧沿径向支承摆动构件。

16. 发明授权

US6095114A Gasoline direct-injection engine 失效
标题翻译：汽油直喷发动机
公开(公告)号：US6095114A
公开(公告)日：2000-08-01
申请号：US304993
申请日：1999-05-04
申请人： Kaoru Horie , Masaki Takayama , Hitoshi Takahashi , Hiromi Matsuura , Susumu Nakajima , Naoaki Takeda , Mitsuharu Imaseki
发明人： Kaoru Horie , Masaki Takayama , Hitoshi Takahashi , Hiromi Matsuura , Susumu Nakajima , Naoaki Takeda , Mitsuharu Imaseki
IPC分类号： F02B17/00 , F02B23/10 , F02B75/12 , F02F1/42 , F02F3/00 , F02F3/26 , F02M61/14 , F02R17/00
CPC分类号： F02B23/101 , F02F1/4214 , F02B2023/102 , F02B2023/108 , F02B2075/125 , Y02T10/123 , Y02T10/125 , Y02T10/146
摘要： A gasoline direct-injection engine includes a cavity provided in a top portion of a piston and constituting a portion of a combustion chamber defined between a cylinder head and the top portion of the piston, a fuel injection valve mounted in the cylinder head for injecting gasoline directly into the combustion chamber, and a spark plug also mounted in the cylinder head to face the combustion chamber. In this gasoline direct-injection engine, the fuel injection valve facing a substantially central portion of a ceiling surface of the combustion chamber is mounted in the cylinder head to have an axis substantially parallel to an axis of the piston, and the cavity provided in the top portion of the piston and disposed below the fuel injection valve and the spark plug is defined so that it is deeper in an area corresponding to the spark plug than in an area corresponding to the fuel injection valve. Thus, it is possible to achieve a stable lean laminar burn in wide ranges of rotational speed and load of the engine, thereby providing an improvement in fuel consumption and an enhancement in nature of an exhaust gas.
摘要翻译：汽油直喷发动机包括设置在活塞的顶部并构成燃烧室的一部分的空腔，所述燃烧室限定在气缸盖和活塞的顶部之间，燃料喷射阀安装在用于喷射汽油的气缸盖中直接进入燃烧室，以及还安装在气缸盖中以面向燃烧室的火花塞。在该汽油直喷发动机中，燃料喷射阀面对燃烧室顶面的大致中央部分安装在气缸盖中，具有基本上平行于活塞轴线的轴线，活塞的顶部并且设置在燃料喷射阀下方，并且火花塞被限定为使得其在对应于火花塞的区域中比在对应于燃料喷射阀的区域更深。因此，可以在发动机的转速和负载的宽范围内实现稳定的薄层层状燃烧，从而提供燃料消耗的改善和排气性质的提高。

17. 发明授权

US5813429A Compressed natural gas charging system 失效
标题翻译：压缩天然气充气系统
公开(公告)号：US5813429A
公开(公告)日：1998-09-29
申请号：US606000
申请日：1996-02-09
申请人： Akifumi Ohtaka , Hiroshi Shimanuki , Hiromi Matsuura , Masayuki Tsuchiya
发明人： Akifumi Ohtaka , Hiroshi Shimanuki , Hiromi Matsuura , Masayuki Tsuchiya
IPC分类号： F17C13/00 , F17C5/06 , F17C13/04 , F16K17/38
CPC分类号： F17C5/06 , F17C2201/0119 , F17C2201/056 , F17C2205/0134 , F17C2205/0335 , F17C2205/0338 , F17C2205/0394 , F17C2209/234 , F17C2221/033 , F17C2223/0123 , F17C2223/036 , F17C2227/0304 , F17C2250/0434 , F17C2260/025 , F17C2265/066 , F17C2270/0168 , F17C2270/0178 , Y10T137/4857 , Y10T137/6606 , Y10T137/7904
摘要： A compressed natural gas charging system includes a gas charging passageway whose one end is capable of being connected to a compressed natural gas supply device capable of supplying a compressed natural gas and whose other end opens into a gas vessel, and a one-way valve incorporated in the gas charging passageway to permit the compressed natural gas to flow from the one end of the gas charging passage through the one-way valve toward the other end. In the compressed natural gas charging system, a constriction is provided in the gas charging passageway downstream of the one-way valve and has a constriction degree larger than that of the one-way valve. Thus, it is possible to prevent an excessive temperature drop due to the adiabatic expansion of the compressed natural gas from occurring across the one-way valve and to rapidly charge the compressed natural gas, and it is unnecessary to use an expensive material for a part of or constituting the one-way valve.
摘要翻译：压缩天然气充气系统包括气体充气通道，其一端能够连接到能够供应压缩天然气并且其另一端打开到气体容器中的压缩天然气供应装置，并且单向阀并入在气体充气通道中，允许压缩的天然气从气体充填通道的一端通过单向阀向另一端流动。在压缩天然气充填系统中，在单向阀下游的气体充气通道中设置有收缩度大于单向阀的收缩度。因此，可以防止由于压缩天然气的绝热膨胀而在单向阀上发生的过度的温度下降并且使压缩的天然气迅速充电，并且不需要使用昂贵的材料用于零件或组成单向阀。

18. 发明授权

US5735248A Fuel injection method for gas fuel engine 失效
标题翻译：燃气发动机燃油喷射方法
公开(公告)号：US5735248A
公开(公告)日：1998-04-07
申请号：US698519
申请日：1996-08-15
申请人： Hiromi Matsuura , Hideki Minami , Susumu Nakajima , Kazuhiro Ueda , Shigeru Aoki , Toshiyuki Nishida
发明人： Hiromi Matsuura , Hideki Minami , Susumu Nakajima , Kazuhiro Ueda , Shigeru Aoki , Toshiyuki Nishida
IPC分类号： F02M21/02 , F02D19/02 , F02D41/02
CPC分类号： F02D19/027 , F02D19/024 , F02M21/0224 , F02M21/0278 , Y02T10/32
摘要： A fuel injection method wherein optimum fuel injection timing in a fuel-injection type gas fuel engine is determined by setting fuel injection end timing to be after the start of opening of an intake valve. That is, when injection ends in a first half of the intake valve open period the volumetric efficiency .eta.v falls and the engine output also falls, because the injection period overlaps with a period of positive pressure arising inside the intake pipe before opening of the intake valve, but when injection ends in a second half of the intake valve open period the volumetric efficiency .eta.v rises and the engine efficiency also rises, because the injection period overlaps with a period of negative pressure arising in the intake pipe during the first half of the intake value open period. Consequently, when fuel is injected during this trough in the intake port pressure, the volumetric efficiency increases and the engine output also increases by several percent.
摘要翻译：一种燃料喷射方法，其中燃料喷射型气体燃料发动机中的最佳燃料喷射正时通过将燃料喷射结束定时设定为在开阀开始之后。也就是说，当进气阀打开期间的前半部分的喷射结束时，体积效率等级下降，并且发动机输出也下降，因为喷射周期与在进气口打开之前在进气管内部产生的正压时间重叠但是当喷射在进气阀打开时段的后半段结束时，容积效率η升高并且发动机效率也上升，因为喷射周期与进气管在上半年期间产生的负压时间重叠摄入量开放期。因此，当在进气口压力期间在该槽内喷射燃料时，容积效率增加，发动机输出也增加了几个百分点。

19. 发明授权

US5596537A Semiconductor device test circuit having test enable circuitry and test mode-entry circuitry 失效
标题翻译：具有测试使能电路和测试模式进入电路的半导体器件测试电路
公开(公告)号：US5596537A
公开(公告)日：1997-01-21
申请号：US275700
申请日：1994-07-14
申请人： Shunichi Sukegawa , Shiyuzo Shiozaki , Hiromi Matsuura , Masaya Muranaka
发明人： Shunichi Sukegawa , Shiyuzo Shiozaki , Hiromi Matsuura , Masaya Muranaka
IPC分类号： G11C29/00 , G11C29/14 , G11C29/46 , G11C7/00
CPC分类号： G11C29/46
摘要： A semiconductor device test circuit for inclusion on a semiconductor chip having a semiconductor device thereon, wherein a test mode with respect to the semiconductor device is not entered during normal use of the semiconductor device and the test mode can be entered without applying a voltage higher than the power supply voltage to an external terminal of the semiconductor device. The test circuit includes a decoder circuit which detects the matching of a first address input corresponding to a test mode, and a latch circuit which latches the signal indicating the matching of the first address input with a test mode. A second decoder circuit then detects the matching of a second address to the test mode, the second address being input when the matching signal for the first address has been latched. A second latch circuit latches the signal indicating the matching of the second address. A third address input is processed by a third decoder circuit and a third latch circuit in the same way. This means that when a plurality of addresses (three addresses in the described example) which are consecutively input to the respective decoder circuits are in a predetermined, specific combination, a test enable signal is output and the test mode is activated.
摘要翻译：一种用于包含在其上具有半导体器件的半导体芯片上的半导体器件测试电路，其中在半导体器件的正常使用期间不进入相对于半导体器件的测试模式，并且可以进入测试模式而不施加高于对半导体器件的外部端子的电源电压。测试电路包括检测与测试模式相对应的第一地址输入的匹配的解码器电路和锁存指示第一地址输入与测试模式匹配的信号的锁存电路。第二解码器电路然后检测第二地址与测试模式的匹配，当第一地址的匹配信号被锁存时，第二地址被输入。第二锁存电路锁存指示第二地址匹配的信号。第三地址输入由第三解码器电路和第三锁存电路以相同的方式处理。这意味着当连续输入到各个解码器电路的多个地址（所述示例中的三个地址）处于预定的特定组合时，输出测试使能信号并且测试模式被激活。

20. 发明授权

US5217917A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5217917A
公开(公告)日：1993-06-08
申请号：US496280
申请日：1990-03-20
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

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