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11. 发明授权

US09423847B2 Method and apparatus for transitioning a system to an active disconnect state 有权
标题翻译：用于将系统转换到主动断开状态的方法和装置
公开(公告)号：US09423847B2
公开(公告)日：2016-08-23
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S Bernucho , Maurice B Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

12. 发明授权

US09417679B2 Adaptive connected standby for a computing device 有权
标题翻译：计算设备的自适应连接待机
公开(公告)号：US09417679B2
公开(公告)日：2016-08-16
申请号：US13674476
申请日：2012-11-12
申请人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
发明人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3212 , G06F1/3287 , Y02D10/171 , Y02D10/174
摘要： Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.
摘要翻译：公开了各种计算设备和管理功耗的方法。一方面，提供一种管理具有电池的计算装置的功耗的方法。该方法包括在连接的待机活动状态和连接的待机空闲状态之间循环计算设备。连接的待机空闲状态的持续时间至少部分地基于电池的充电水平来设定。

13. 发明授权

US09383801B2 Methods and apparatus related to processor sleep states 有权
标题翻译：与处理器睡眠状态有关的方法和设备
公开(公告)号：US09383801B2
公开(公告)日：2016-07-05
申请号：US13725014
申请日：2012-12-21
申请人： Alexander J. Branover , Andrew W. Lueck , Paul E. Kitchin , David A. Kaplan
发明人： Alexander J. Branover , Andrew W. Lueck , Paul E. Kitchin , David A. Kaplan
IPC分类号： G06F1/32
CPC分类号： G06F1/3234
摘要： A system includes a processor including at least a first core and a local interrupt controller associated with the first core. The first core is operable to store its architectural state prior to entering a first core sleep state, and the processor is operable to receive and implement a request for entering a system sleep state in which the first core is in the first core sleep state and the local interrupt controller is powered down and exit the system sleep state by restoring the local interrupt controller and restoring the saved architectural state of the first core.
摘要翻译：系统包括处理器，该处理器至少包括与第一核心相关联的第一核心和本地中断控制器。第一核心可操作以在进入第一核心睡眠状态之前存储其架构状态，并且处理器可操作以接收和实施用于进入其中第一核心处于第一核心睡眠状态的系统睡眠状态的请求，局部中断控制器掉电并退出系统休眠状态，通过恢复本地中断控制器并恢复第一个内核的保存架构状态。

14. 发明授权

US09075609B2 Power controller, processor and method of power management 有权
标题翻译：电源控制器，处理器和电源管理方法
公开(公告)号：US09075609B2
公开(公告)日：2015-07-07
申请号：US13327380
申请日：2011-12-15
申请人： William Lloyd Bircher , Alexander J. Branover
发明人： William Lloyd Bircher , Alexander J. Branover
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3243 , G06F1/329 , Y02D10/152 , Y02D10/24
摘要： A processor includes a plurality of exclusive resources, a shared resource, and a controller configured to manage power state transitions of each of the plurality of exclusive resources and the shared resource. The controller receives a request from a resource to transition from a first power state to a lower power state and, in response to receiving the request, the controller controls power state transitions of the resource according to a first power control threshold when the resource is one of the plurality of exclusive resources and according to a second power control threshold that is greater than the first power control threshold when the resource is the shared resource.
摘要翻译：处理器包括多个独占资源，共享资源和被配置为管理多个独占资源和共享资源中的每一个的功率状态转换的控制器。所述控制器从资源接收到从第一功率状态转换到较低功率状态的请求，并且响应于接收到所述请求，所述控制器在所述资源为一个时根据第一功率控制阈值来控制所述资源的功率状态转换的多个独占资源，并且当资源是共享资源时，根据大于第一功率控制阈值的第二功率控制阈值。

15. 发明授权

US08924758B2 Method for SOC performance and power optimization 有权
标题翻译： SOC性能和功率优化方法
公开(公告)号：US08924758B2
公开(公告)日：2014-12-30
申请号：US13360012
申请日：2012-01-27
申请人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
发明人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.
摘要翻译：一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。诸如片上系统（SOC）的集成电路包括至少两个处理单元。第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

16. 发明授权

US08862909B2 System and method for determining a power estimate for an I/O controller based on monitored activity levels and adjusting power limit of processing units by comparing the power estimate with an assigned power limit for the I/O controller 有权
标题翻译：通过将功率估计与I / O控制器的分配的功率限制进行比较，基于监视的活动水平和调整处理单元的功率限制来确定I / O控制器的功率估计的系统和方法
公开(公告)号：US08862909B2
公开(公告)日：2014-10-14
申请号：US13310231
申请日：2011-12-02
申请人： Alexander J. Branover , Madhu Saravana Sibi Govindan , Guhan Krishnan , Hemant R. Mohapatra , Andrew W. Lueck
发明人： Alexander J. Branover , Madhu Saravana Sibi Govindan , Guhan Krishnan , Hemant R. Mohapatra , Andrew W. Lueck
IPC分类号： G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/32 , G06F1/00 , G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126
摘要： A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference.
摘要翻译：一种用于高效管理IC内的运行模式以实现最佳功率和性能目标的系统和方法。在相同的芯片上，SOC包括一个或多个处理单元和输入/输出（I / O）控制器（IOC）。 IOC中的多个接口根据多种不同的协议管理数据包和消息。 IOC维护多个接口中的每一个的活动级别。该活动级别可以至少基于由多个接口中的相应一个执行的事务的相应数量。至少基于活动水平，国际奥委会决定自己的能力估计。响应于检测到功率估计与IOC的分配的I / O功率限制之间的差异，功率管理器至少基于差异来调整至少相应的一个或多个处理单元的功率限制。

17. 发明申请

US20130159755A1 APPARATUS AND METHOD FOR MANAGING POWER ON A SHARED THERMAL PLATFORM FOR A MULTI-PROCESSOR SYSTEM 有权
标题翻译：用于管理用于多处理器系统的共享热平台的功率的装置和方法
公开(公告)号：US20130159755A1
公开(公告)日：2013-06-20
申请号：US13329988
申请日：2011-12-19
申请人： Stephen D. Presant , Alexander J. Branover , Oleksandr Khodorkovsky , Ljubisa Bajic
发明人： Stephen D. Presant , Alexander J. Branover , Oleksandr Khodorkovsky , Ljubisa Bajic
IPC分类号： G06F1/00
CPC分类号： G06F9/5094 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/22
摘要： A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.
摘要翻译：一种方法和装置包括具有共享热平台的多个集成电路处理器的多处理器装置。每个处理器具有至少一个可在多个不同功率设置下工作的子系统，至少一个内部热参数检测器，提供与处理器相关的功率数据，以及功率管理单元。该方法和装置示例性地在多个处理器的功率管理单元之间共享来自每个处理器的至少一个内部热参数检测器的功率数据; 将来自所述多个处理器的共享功率数据与所述共享热平台的热设计功率限制进行比较; 并且基于共享功率数据与共享热平台的热设计功率限制的比较来控制共享热平台内的多个处理器的至少一个子系统的功率设置。

18. 发明申请

US20130151869A1 METHOD FOR SOC PERFORMANCE AND POWER OPTIMIZATION 有权
标题翻译：用于SOC性能和功率优化的方法
公开(公告)号：US20130151869A1
公开(公告)日：2013-06-13
申请号：US13360012
申请日：2012-01-27
申请人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
发明人： Maurice B. Steinman , Alexander J. Branover , Guhan Krishnan
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/324 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A system and method for efficient management of resources within a semiconductor chip for an optimal combination of power reduction and high performance. An intergrated circuit, such as a system on a chip (SOC), includes at least two processing units. The second processing unit includes a cache. The SOC includes a power management unit (PMU) that determines whether a first activity level for the first processing unit is above a first threshold and a second activity level for the second processing unit is below a second threshold. If this condition is true, then the PMU places a limit on a highest power-performance state (P-state) used by the second processing unit. The PMU sends an indication to flush the at least one cache within the second processing unit. The PMU changes a P-state used by the first processing unit to a higher performance P-state.
摘要翻译：一种用于有效管理半导体芯片内的资源以实现功率降低和高性能的最佳组合的系统和方法。诸如片上系统（SOC）的集成电路包括至少两个处理单元。第二处理单元包括高速缓存。 SOC包括功率管理单元（PMU），其确定第一处理单元的第一活动级别是否高于第一阈值，并且第二处理单元的第二活动级别低于第二阈值。如果该条件为真，则PMU对第二处理单元使用的最高功率状态（P状态）设置限制。 PMU发送指示以刷新第二处理单元内的至少一个高速缓存。 PMU将第一处理单元使用的P状态改变为更高性能的P状态。

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