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11. 发明申请

US20140019723A1 BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：不对称多处理器系统中的二进制翻译
公开(公告)号：US20140019723A1
公开(公告)日：2014-01-16
申请号：US13993042
申请日：2011-12-28
申请人： Koichi Yamada , Ronny Ronen , Wei Li , Boris Ginzburg , Gadi Haber , Konstantin Levit-Gurevich , Esfir Natanzon , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
发明人： Koichi Yamada , Ronny Ronen , Wei Li , Boris Ginzburg , Gadi Haber , Konstantin Levit-Gurevich , Esfir Natanzon , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F1/3243 , G06F1/3293 , G06F9/30174 , G06F9/3808 , G06F9/4552 , G06F9/5094 , G06F15/7807 , Y02D10/122 , Y02D10/152 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。分析用于在ASMP上执行的程序代码，并且确定是否允许程序代码或其代码段在本地上在第一核上执行或者对代码使用二进制转换并且在在执行过程中消耗的功率比第一个核心少的第二个核心。

12. 发明申请

US20140068302A1 MECHANISM FOR FACILITATING FASTER SUSPEND/RESUME OPERATIONS IN COMPUTING SYSTEMS 有权
标题翻译：促进计算机系统中更快的停机/恢复运行的机制
公开(公告)号：US20140068302A1
公开(公告)日：2014-03-06
申请号：US13596915
申请日：2012-08-28
申请人： Ohad Falik , Eliezer Weissmann , Alon Naveh , Michael Mishaeli , Nadav Shulman , Robert E. Gough , Erik C. Bjorge , Douglas R. Moran , Peter A. Dice
发明人： Ohad Falik , Eliezer Weissmann , Alon Naveh , Michael Mishaeli , Nadav Shulman , Robert E. Gough , Erik C. Bjorge , Douglas R. Moran , Peter A. Dice
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F9/4418
摘要： A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.
摘要翻译：描述了根据本发明的一个实施例的用于促进计算系统中更快的挂起/恢复操作的机制。本发明的实施例的方法包括：响应于在计算系统处的睡眠呼叫，将起始进程启动到第一睡眠状态，从第一休眠状态转换到第二休眠状态。转换可以包括在与计算系统处理器的一个或多个处理器核心相关联的本地存储器处保留处理器上下文的至少一部分。该方法还可以包括进入第二睡眠状态。

13. 发明申请

US20130268742A1 CORE SWITCHING ACCELERATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM 有权
标题翻译：不对称多处理器系统中的核心切换加速
公开(公告)号：US20130268742A1
公开(公告)日：2013-10-10
申请号：US13992710
申请日：2011-12-29
申请人： Koichi Yamada , Boris Ginzburg , Wei Li , Ronny Ronen , Esfir Natanzon , Konstantin Levit-Gurevich , Gadi Haber , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
发明人： Koichi Yamada , Boris Ginzburg , Wei Li , Ronny Ronen , Esfir Natanzon , Konstantin Levit-Gurevich , Gadi Haber , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/5044 , G06F9/5094 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。可以进行选择以提供程序代码的本地执行，以最小化功耗等等。可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。然后由ASMP执行检测的程序代码。

14. 发明授权

US09348594B2 Core switching acceleration in asymmetric multiprocessor system 有权
标题翻译：非对称多处理器系统中的核心切换加速
公开(公告)号：US09348594B2
公开(公告)日：2016-05-24
申请号：US13992710
申请日：2011-12-29
申请人： Koichi Yamada , Boris Ginzburg , Wei Li , Ronny Ronen , Esfir Natanzon , Konstantin Levit-Gurevich , Gadi Haber , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
发明人： Koichi Yamada , Boris Ginzburg , Wei Li , Ronny Ronen , Esfir Natanzon , Konstantin Levit-Gurevich , Gadi Haber , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
IPC分类号： G06F9/40 , G06F9/30 , G06F9/50
CPC分类号： G06F9/30181 , G06F9/5044 , G06F9/5094 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。可以进行选择以提供程序代码的本地执行，以最小化功耗等等。可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。然后由ASMP执行检测的程序代码。

15. 发明申请

US20140013333A1 CONTEXT-STATE MANAGEMENT 有权
标题翻译：背景状态管理
公开(公告)号：US20140013333A1
公开(公告)日：2014-01-09
申请号：US13993471
申请日：2011-12-28
申请人： Michael Mishaeli , James B. Crossland , Boris Ginzburg , Eliezer Weissmann
发明人： Michael Mishaeli , James B. Crossland , Boris Ginzburg , Eliezer Weissmann
IPC分类号： G06F9/46
CPC分类号： G06F9/461 , G06F9/44 , G06F9/445 , G06F9/46 , G06F9/48
摘要： Extended features such as registers and functions within processors are made available to operating systems (OS) using an extended-state driver and by modifying instruction set extensions, such as XSAVE. A map-table designates a correspondence between memory locations for storing data relating to extended features not supported by the OS and called by an application. As a result, applications may utilize processor resources which are unsupported by the OS.
摘要翻译：扩展功能（如处理器内的寄存器和功能）可以使用扩展状态驱动程序和修改指令集扩展（如XSAVE）对操作系统（OS）可用。映射表指定用于存储与OS不支持并被应用程序调用的扩展特征有关的数据的存储器位置之间的对应关系。因此，应用程序可能利用OS不支持的处理器资源。

16. 发明申请

US20130346728A1 Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令性能
公开(公告)号：US20130346728A1
公开(公告)日：2013-12-26
申请号：US14012344
申请日：2013-08-28
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

17. 发明申请

US20070150703A1 Breaking a lock situation in a system 有权
标题翻译：打破系统中的锁定情况
公开(公告)号：US20070150703A1
公开(公告)日：2007-06-28
申请号：US11301058
申请日：2005-12-12
申请人： Avi Mendelson , Michael Mishaeli , Julius Mandelblat
发明人： Avi Mendelson , Michael Mishaeli , Julius Mandelblat
IPC分类号： G06F9/30
CPC分类号： G06F9/524
摘要： In one embodiment, the present invention includes a method including initiating a cleaning operation to clear a first processor core of a system of pending operations, and preventing injection of new events into a second processor core if the cleaning operation is not serviced in the first processor core. In this way, lock situations may be broken without their detection. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种方法，包括启动清理操作以清除待处理操作的系统的第一处理器核心，以及如果在第一处理器中没有服务于清洁操作，则防止将新事件注入到第二处理器核心核心。以这种方式，锁定情况可能在没有检测到的情况下被破坏。描述和要求保护其他实施例。

18. 发明授权

US09519324B2 Local power gate (LPG) interfaces for power-aware operations 有权
标题翻译：用于电源感知操作的本地电源门（LPG）接口
公开(公告)号：US09519324B2
公开(公告)日：2016-12-13
申请号：US14225612
申请日：2014-03-26
申请人： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
发明人： Michael Mishaeli , Ron Gabor , Robert C. Valentine , Alex Gerber , Zeev Sperber
IPC分类号： G06F1/32 , G06F9/22
CPC分类号： G06F1/3206 , G06F1/3287 , G06F9/22 , Y02D10/171
摘要： Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.
摘要翻译：描述了用于功率感知操作的本地电源门（LPG）接口的技术。处理器包括核心的本地门控电路，核心的主核心电路，主核心和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为本地门控电路供电。主核心解码一组指令的第一指令以执行指定长度的第一功率感知操作，包括计算用于执行的执行代码路径。主核心监控LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择其中一条代码路径，并向LPG硬件发出提示，以启动本地并且继续执行第一功率感知操作，而不等待本地门控电路被加电。

19. 发明申请

US20130219154A1 CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS 有权
公开(公告)号：US20130219154A1
公开(公告)日：2013-08-22
申请号：US13837923
申请日：2013-03-15
申请人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
发明人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30003 , G06F9/30101 , G06F9/461
摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

20. 发明申请

US20100115240A1 Optimizing performance of instructions based on sequence detection or information associated with the instructions 有权
标题翻译：基于序列检测或与指令相关的信息优化指令的性能
公开(公告)号：US20100115240A1
公开(公告)日：2010-05-06
申请号：US12290962
申请日：2008-11-05
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30 , G06F12/06
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一个指令解码器，其可以接收输入指令和路径选择信号，并且响应于路径选择信号将输入指令解码为第一指令代码或第二指令代码。代表相同输入指令的两个不同的指令代码可以被执行单元用于执行针对不同数据长度优化的操作。描述和要求保护其他实施例。

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