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11. 发明申请

US20060092715A1 Circuit 有权
标题翻译：电路
公开(公告)号：US20060092715A1
公开(公告)日：2006-05-04
申请号：US11099222
申请日：2005-04-05
申请人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
发明人： Georg Braun , Maksim Kuzmenka , Hermann Ruckerbauer
IPC分类号： G11C7/10
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1093 , G11C7/14
摘要： A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.
摘要翻译：电路呈现信号输入，用于基于在信号输入处接收的信号的特性来确定参考电平的装置。此外，电路还具有用于基于参考电平来评估信号的装置。

12. 发明授权

US06759874B2 Electronic circuit with a driver circuit 有权
标题翻译：具有驱动电路的电子电路
公开(公告)号：US06759874B2
公开(公告)日：2004-07-06
申请号：US10253001
申请日：2002-09-23
申请人： Georg Braun , Helmut Kandolf
发明人： Georg Braun , Helmut Kandolf
IPC分类号： H03K19094
CPC分类号： H03K19/0005
摘要： An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.
摘要翻译：电子电路具有将信号驱动到信号线上的驱动电路。驱动器电路包括第一开关器件，其具有在第一电源电压端子和信号线之间的第一正向电阻，以及在第二电源电压端子和信号线之间具有第二正向电阻的第二开关器件。提供控制电路以产生第一和第二控制信号，以在第一操作模式下控制第一和第二开关装置，使得根据待驱动的信号，第一开关装置或第二开关装置是通过连接。在第二操作模式中，第一开关器件和第二开关器件借助于第一和第二控制信号基本上被连接，使得第一和第二正向电阻一起形成终止电阻。

13. 发明授权

US06469571B2 Charge pump with charge equalization for improved efficiency 有权
标题翻译：电荷泵具有电荷均衡以提高效率
公开(公告)号：US06469571B2
公开(公告)日：2002-10-22
申请号：US09996280
申请日：2001-11-28
申请人： Robert Esterl , Georg Braun
发明人： Robert Esterl , Georg Braun
IPC分类号： G05F302
CPC分类号： H02M3/073
摘要： A charge pump has two inputs, each for an input clock signal, and an output for the output of a pumped output potential. Two pumping capacitors are connected to the inputs. Second electrodes of the pumping capacitors are in each case connected via a first circuit module to a supply potential (ground) and via a second circuit module to the output. Also present is a controllable short-circuiting element, the controllable path of which is disposed between the second electrodes of the two pumping capacitors.
摘要翻译：电荷泵具有两个输入，每个输入用于输入时钟信号，以及用于输出泵浦输出电位的输出。两个泵浦电容器连接到输入端。泵送电容器的第二电极在每种情况下都经由第一电路模块连接到电源（地），并且经由第二电路模块连接到输出端。还存在可控短路元件，其可控路径设置在两个泵浦电容器的第二电极之间。

14. 发明授权

US06327173B2 Method for writing and reading a ferroelectric memory 有权
公开(公告)号：US06327173B2
公开(公告)日：2001-12-04
申请号：US09740637
申请日：2000-12-18
申请人： Georg Braun
发明人： Georg Braun
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A method is described for reading and writing a ferroelectric memory. In ferroelectric memories, changes in a hysteresis curve on account of aging of the ferroelectric material are reduced or prevented by virtue of the fact that during reading and writing a complementary state is also written in and a capacitor voltage is reduced to 0 V before a memory cell is deactivated.

15. 发明授权

US6091625A Ferroelectric memory and method for preventing aging in a memory cell 有权
标题翻译：铁电存储器和用于防止存储器单元中的老化的方法
公开(公告)号：US6091625A
公开(公告)日：2000-07-18
申请号：US408479
申请日：1999-09-28
申请人： Georg Braun , Carlos Mazure-Espejo , Heinz Honigschmid , Andrej Majdic
发明人： Georg Braun , Carlos Mazure-Espejo , Heinz Honigschmid , Andrej Majdic
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit. The switching state of the switching unit is changed at least once during a write access operation, so that the information to be written is written to the relevant memory cell by the first sense amplifier initially in noninverted form and then in inverted form. A method for preventing aging in a memory cell in an integrated memory is also provided.
摘要翻译：集成存储器包括具有位线，字线和可写存储单元的单元阵列。第一差分读出放大器具有连接到数据线对的连接，第一读出放大器在读访问操作期间从存储器单元之一读取信息，以便随后对其进行放大，并且第一读出放大器将信息写入一个的存储单元。相关信息通过数据线对传送为差分信号，并且在每次写入操作期间由第一读出放大器临时存储。存储器还具有开关单元，通过该开关单元，数据线对连接到第一读出放大器的连接，用于相对于第一读出放大器的连接交换数据线对的线，这取决于开关状态开关单元。切换单元的切换状态在写访问操作期间至少改变一次，使得要被写入的信息由第一读出放大器最初以非反相的形式被写入相关存储器单元，然后以倒置形式写入相关的存储单元。还提供了一种用于防止集成存储器中的存储单元中的老化的方法。

16. 发明授权

US07844798B2 Command protocol for integrated circuits 有权
标题翻译：集成电路命令协议
公开(公告)号：US07844798B2
公开(公告)日：2010-11-30
申请号：US11955659
申请日：2007-12-13
申请人： Andreas Gärtner , Georg Braun , Maurizio Skerlj , Johannes Stecker
发明人： Andreas Gärtner , Georg Braun , Maurizio Skerlj , Johannes Stecker
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G11C8/12 , G11C2207/2227 , Y02D10/14 , Y02D10/171
摘要： A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that provides additional information about the operation to be performed. The attributes portion of the command is supplied to the integrated circuit with a delay relative to the instruction portion of the command. The integrated circuit selectively enables circuitry for processing the attributes portion if the integrated circuit determines from the received instruction portion that the command also includes an attributes portion. The delay between the two portions of the command provides sufficient time for the integrated circuit to enable the attributes processing circuitry, which, in a default state, can be disabled during an active mode of the integrated circuit to save power.
摘要翻译：一种操作集成电路的方法包括向集成电路提供命令的指令部分，以指定要由集成电路执行的操作。至少一些类型的命令还包括提供关于要执行的操作的附加信息的属性部分。命令的属性部分相对于命令的指令部分延迟地提供给集成电路。如果集成电路从接收到的指令部分确定该命令还包括属性部分，则集成电路选择性地启用用于处理属性部分的电路。该命令的两个部分之间的延迟为集成电路提供了足够的时间，使得能够在集成电路的活动模式期间在默认状态下禁用属性处理电路以节省功率。

17. 发明授权

US07532523B2 Memory chip with settable termination resistance circuit 有权
标题翻译：内存芯片，可设置终端电阻电路
公开(公告)号：US07532523B2
公开(公告)日：2009-05-12
申请号：US11461380
申请日：2006-07-31
申请人： Georg Braun , Christian Weis , Eckehard Plaettner
发明人： Georg Braun , Christian Weis , Eckehard Plaettner
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G06F13/4086 , G11C5/04
摘要： Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.
摘要翻译：用于设置存储芯片的各种终端的方法和装置。存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口以及连接到终端的控制电路电路，以便根据接收到的控制命令信号设置电阻值。

18. 发明授权

US07149864B2 Method and circuit for allocating memory arrangement addresses 有权
标题翻译：分配存储器配置地址的方法和电路
公开(公告)号：US07149864B2
公开(公告)日：2006-12-12
申请号：US10777992
申请日：2004-02-12
申请人： Georg Braun , Andreas Jakobs
发明人： Georg Braun , Andreas Jakobs
IPC分类号： G06F12/02
CPC分类号： G06F12/0669
摘要： Methods and apparatus for allocating memory arrangement addresses to a buffer chip, during an initialization mode, for use in addressing one or more memory arrangements connected to the buffer chip are provided. A buffer circuit may receive first initialization data specifying a first set of available memory arrangement addresses and associate one or more of the first set of available memory arrangement addresses with the one or more memory arrangements connected to the buffer chip. The buffer circuit may also generate second initialization data specifying the set of available memory arrangement addresses available after the association. The second initialization data may be transmitted to another buffer circuit for use in address allocation or back to a memory access control unit.
摘要翻译：提供了用于在初始化模式期间将存储器布置地址分配给缓冲器芯片用于寻址连接到缓冲器芯片的一个或多个存储器配置的方法和装置。缓冲器电路可以接收指定第一组可用存储器布置地址的第一初始化数据，并将第一组可用存储器配置地址中的一个或多个与连接到缓冲器芯片的一个或多个存储器配置相关联。缓冲电路还可以产生指定在关联之后可用的可用存储器布置地址的集合的第二初始化数据。第二初始化数据可以被发送到用于地址分配的另一缓冲电路或者返回到存储器访问控制单元。

19. 发明申请

US20060262613A1 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US20060262613A1
公开(公告)日：2006-11-23
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

20. 发明授权

US07139290B2 Transmitting data into a memory cell array 有权
公开(公告)号：US07139290B2
公开(公告)日：2006-11-21
申请号：US10171098
申请日：2002-06-13
申请人： Georg Braun
发明人： Georg Braun
IPC分类号： H04J3/08 , G11C8/00
CPC分类号： G11C7/1087 , G11C7/1006 , G11C7/1078
摘要： A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a control signal, thereby dividing the data stream into a storage data stream and a mask data stream. The storage data stream is then buffered into a register unit, where it is divided into data stream components buffered in corresponding data register components on the basis of a clock signal and an address signal provided to the register unit. Meanwhile, the mask data stream is buffered in a mask register of the register unit. A composite data stream is then formed by combining selected data stream components in response to information provided by a data mask unit from the mask data stream buffered in the mask register. Data corresponding to this composite data stream is then provided to the memory cell array for storage therein.

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