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1. 发明授权

US07532523B2 Memory chip with settable termination resistance circuit 有权
标题翻译：内存芯片，可设置终端电阻电路
公开(公告)号：US07532523B2
公开(公告)日：2009-05-12
申请号：US11461380
申请日：2006-07-31
申请人： Georg Braun , Christian Weis , Eckehard Plaettner
发明人： Georg Braun , Christian Weis , Eckehard Plaettner
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G06F13/4086 , G11C5/04
摘要： Methods and apparatus for setting various terminations of a memory chip. The memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.
摘要翻译：用于设置存储芯片的各种终端的方法和装置。存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口以及连接到终端的控制电路电路，以便根据接收到的控制命令信号设置电阻值。

2. 发明申请

US20060262613A1 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US20060262613A1
公开(公告)日：2006-11-23
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

3. 发明授权

US07457174B2 Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted 有权
标题翻译：半导体存储器和方法，用于在接收要发送的写入数据期间适配时钟信号和选通信号之间的相位关系
公开(公告)号：US07457174B2
公开(公告)日：2008-11-25
申请号：US11410320
申请日：2006-04-24
申请人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
发明人： Georg Braun , Eckehard Plaettner , Christian Weis , Andreas Jakobs
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method is provided for adapting the phase relationship between a clock signal and a strobe signal for accepting write data to be transmitted into a memory circuit, a write command signal being transmitted to the memory circuit in a manner synchronized with the clock signal, a write data signal being transmitted synchronously with the strobe signal, a phase offset between the transmitted clock signal and the transmitted strobe signal being set such that the write data are reliably accepted in the memory circuit. The method comprises the following acts performed in the memory circuit: generating a write acceptance signal depending on the clock signal and the write command signal with a specific pulse duration; determining the number of edges of the strobe signal with a defined edge direction during the pulse duration; comparing the number determined with a predetermined desired number of corresponding edges of the strobe signal; and providing an item of error information indicating whether the number determined matches the desired number.
摘要翻译：提供了一种适应时钟信号和选通信号之间的相位关系的方法，用于接收要发送到存储器电路的写入数据，写入命令信号以与时钟信号同步的方式发送到存储器电路，写入数据信号与选通信号同步发送，所发送的时钟信号和发送的选通信号之间的相位偏移被设置为使得写入数据被可靠地接受在存储器电路中。该方法包括在存储器电路中执行的以下动作：根据具有特定脉冲持续时间的时钟信号和写入命令信号产生写入验收信号; 在所述脉冲持续时间期间，确定具有限定的边缘方向的所述选通信号的边缘数; 将所选择的所述数量与所述选通信号的相应边缘的预定数量进行比较; 并提供指示所确定的数量是否匹配所需数量的错误信息项。

4. 发明申请

US20070035326A1 MEMORY CHIP AND METHOD FOR OPERATING A MEMORY CHIP 有权
标题翻译：记忆芯片和操作记忆芯片的方法
公开(公告)号：US20070035326A1
公开(公告)日：2007-02-15
申请号：US11461380
申请日：2006-07-31
申请人： Georg Braun , Christian Weis , Eckehard Plaettner
发明人： Georg Braun , Christian Weis , Eckehard Plaettner
IPC分类号： H03K19/003
CPC分类号： G11C7/1048 , G06F13/4086 , G11C5/04
摘要： Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.
摘要翻译：用于设置存储芯片的各种终端的方法和装置。在一个实施例中，存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口，以及控制电路，连接到终端电路，以便根据接收到的控制命令信号设置电阻值。

5. 发明授权

US07066049B2 Wear-free accelerator pedal kick-down switch 失效
标题翻译：无磨损加速踏板踢脚踏开关
公开(公告)号：US07066049B2
公开(公告)日：2006-06-27
申请号：US10787745
申请日：2004-02-27
申请人： Christian Reimann , Christian Weis , Joachim von Willich
发明人： Christian Reimann , Christian Weis , Joachim von Willich
IPC分类号： G01G1/14
CPC分类号： G05G1/30 , B60K26/02 , F16H59/20 , Y10T74/20528 , Y10T74/20534 , Y10T74/2054
摘要： The present invention relates to an accelerator pedal for a motor vehicle, especially one with an automatic gearbox. The pedal includes a pedal arm which in one end area thereof is pivotally mounted about a pivoting axis and which in the other end thereof is provided with a pedal plate which can be impinged upon the force by the driver. When force is exerted upon the pedal plate, the pedal arm can be pivoted into an absolute final position when a kick down switch is actuated, wherein a signal can be produced by the kick down switch and can be fed to a control electronics system. The kick down switch comprises a permanent magnet, the magnet force thereof being used to retain a magnetically conducting component on a magnetic return element whereby the component can be moved away from the magnetic return element as a result of the movement of the pedal arm into an end position.
摘要翻译：本发明涉及一种用于机动车辆的加速器踏板，特别涉及一种具有自动变速箱的加速踏板。该踏板包括一个踏板臂，在其一端部区域围绕枢转轴线枢转地安装，并且在其另一端设置有能够被驾驶员撞击的踏板板。当力被施加到踏板上时，当启动一个脚踏开关时，踏板臂可以枢转到绝对的最终位置，其中一个信号可以由脚踏开关产生，并且可以被馈送到控制电子系统。击穿开关包括永磁体，其磁力被用于将导磁部件保持在磁返回元件上，由此，由于踏板臂移动到磁性返回元件结束位置

6. 发明申请

US20050008684A1 Method of treatment for acne, rosacea and ulcers with taurolidine and/or taurultam in a pharmaceutical composition 审中-公开
标题翻译：在药物组合物中治疗痤疮，酒渣鼻和溃疡与牛磺罗丁和/或牛磺布胺的方法
公开(公告)号：US20050008684A1
公开(公告)日：2005-01-13
申请号：US10616587
申请日：2003-07-10
申请人： Claus Herdeis , Christian Weis
发明人： Claus Herdeis , Christian Weis
IPC分类号： A61K31/54 , A61K9/70
CPC分类号： A61K31/54
摘要： Treatment of a skin disease selected from acne, rosacea, atopical dermatitis, and various ulcers, by topically applying a suitable pharmaceutical composition containing an effective amount of taurolidine, taurultam or a mixture containing both.
摘要翻译：通过局部施用含有有效量的taurolidine，taurultam或含有两者的混合物的合适的药物组合物治疗选自痤疮，酒渣鼻，特应性皮炎和各种溃疡的皮肤疾病。

7. 发明授权

US06717886B2 Control circuit for an S-DRAM 有权
标题翻译：用于S-DRAM的控制电路
公开(公告)号：US06717886B2
公开(公告)日：2004-04-06
申请号：US10248874
申请日：2003-02-26
申请人： Acharya Pramod , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier , Christian Weis
发明人： Acharya Pramod , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1072 , G11C8/18 , G11C11/4076
摘要： Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.
摘要翻译：用于由具有用于存储等待时间值的可编程模式寄存器的由高频时钟信号计时的S-DRAM的数据路径的控制电路; 延迟发生器，用于以可切换的等待时间延迟由内部序列控制器产生的数据路径控制信号; 延迟解码器，其以取决于存储在模式寄存器中的等待时间值的方式切换等待时间发生器，由至少一个信号延迟元件提供，其可由等待时间解码器切换并用于信号延迟具有特定延迟时间的数据路径控制信号，如果存储的等待时间值高，延迟解码器切换相关联的信号延迟元件。

8. 发明授权

US06480024B2 Circuit configuration for programming a delay in a signal path 有权
公开(公告)号：US06480024B2
公开(公告)日：2002-11-12
申请号：US10046395
申请日：2001-10-19
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
IPC分类号： H03K190173
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091
摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

9. 发明授权

US06404699B1 Integrated circuit having a command decoder 有权
标题翻译：具有命令解码器的集成电路
公开(公告)号：US06404699B1
公开(公告)日：2002-06-11
申请号：US09603742
申请日：2000-06-26
申请人： Peter Schrögmeier , Stefan Dietrich , Sabine Schöniger , Christian Weis
发明人： Peter Schrögmeier , Stefan Dietrich , Sabine Schöniger , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1045 , G11C11/4076
摘要： The integrated circuit has an activation decoder whose outputs are connected to the inputs of a command decoder. When an activation signal is at a first logic level, the activation decoder produces at its outputs a command supplied to it from command inputs. When the activation signal is at a second logic level, the activation decoder produces a deactivation command at its outputs irrespective of the command supplied to it from the command inputs. The command decoder does not activate any of its outputs when the deactivation command is being supplied to its inputs. The command decoder activates one of its outputs in each case when a different command is supplied to its inputs.
摘要翻译：集成电路具有激活解码器，其输出端连接到命令解码器的输入端。当激活信号处于第一逻辑电平时，激活解码器在其输出端产生从命令输入提供给它的命令。当激活信号处于第二逻辑电平时，激活解码器在其输出处产生停用命令，而与从命令输入提供给其的命令无关。当向其输入提供停用命令时，命令解码器不会激活其任何输出。当向其输入提供不同的命令时，命令解码器在每种情况下激活其一个输出。

10. 发明授权

US06351419B1 Integrated memory with a block writing function and global amplifiers requiring less space 有权
标题翻译：具有块写入功能的集成存储器和需要较少空间的全局放大器
公开(公告)号：US06351419B1
公开(公告)日：2002-02-26
申请号：US09580986
申请日：2000-05-30
申请人： Stefan Dietrich , Peter Schrögmeier , Sabine Schöniger , Christian Weis
发明人： Stefan Dietrich , Peter Schrögmeier , Sabine Schöniger , Christian Weis
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/06
摘要： An integrated memory has a first operating mode, in which, during each write access, only one of the two global amplifiers is active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, the memory has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.
摘要翻译：集成存储器具有第一操作模式，其中在每个写入期间，两个全局放大器中只有一个是有源的，并且通过一个本地放大器将数据发送到对应的位线。此外，存储器具有第二操作模式，其中在每个写入期间，两个全局放大器同时被激活，并且在每个情况下将至少一个本地放大器的公共数据通路传送到对应的位线。

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