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11. 发明公开

KR1020030090385A 규소층의 표면 처리 방법 및 이를 이용한 박막 트랜지스터기판의 제조 방법 失效
标题翻译：用于处理硅层表面的方法和使用其制造薄膜晶体管基板的方法
公开(公告)号：KR1020030090385A
公开(公告)日：2003-11-28
申请号：KR1020020028668
申请日：2002-05-23
申请人： 삼성전자주식회사
发明人： 강진규 , 이건종 , 이대성 , 한상호 , 차종환 , 홍성수 , 민훈기
IPC分类号： H01L29/786
摘要： PURPOSE: A method for treating the surface of a silicon layer and a method for fabricating a thin film transistor substrate using the same are provided to eliminate particles of an interception layer and a silicon layer and change the surface characteristic of the interception layer and the silicon layer by ozone-treating the surface of the interception layer and the silicon layer. CONSTITUTION: The interception layer is formed on a substrate. The surface of the interception layer is ozone-treated. An amorphous silicon layer is formed on the interception layer. The surface of the amorphous silicon layer is ozone-treated. In the abovementioned ozone treatment, a cleaning process is performed by using O3 and a rinse process is performed by using deionized water.
摘要翻译：目的：提供一种处理硅层表面的方法和使用其制造薄膜晶体管基板的方法，以消除截取层和硅层的颗粒，并改变截取层和硅的表面特性层，通过臭氧处理截取层和硅层的表面。构成：在基板上形成截取层。拦截层的表面经过臭氧处理。在截取层上形成非晶硅层。非晶硅层的表面经过臭氧处理。在上述臭氧处理中，使用O 3进行清洗处理，通过使用去离子水进行漂洗处理。

12. 发明公开

KR1020030088560A 박막 트랜지스터 어레이 기판의 제조 방법 失效
标题翻译：制造薄膜晶体管阵列基板的方法
公开(公告)号：KR1020030088560A
公开(公告)日：2003-11-20
申请号：KR1020020026217
申请日：2002-05-13
申请人： 삼성전자주식회사
发明人： 차종환 , 민훈기 , 이대성
IPC分类号： G02F1/136
CPC分类号： G02F1/136 , G02F1/133553 , G02F2001/13625 , H01L27/1214 , H01L29/786
摘要： PURPOSE: A method for manufacturing a thin film transistor array substrate is provided to sufficiently secure maintenance capacitance while minimizing parasitic capacitance by slightly patterning first interlayer insulating layer on a maintenance electrode wire in forming contact holes. CONSTITUTION: A first interlayer insulating layer(801) formed of an insulating material having a low dielectric constant is formed on a gate insulating layer(140) where gate wires(123) and maintenance electrode wires(131,133) are formed. The first interlayer insulating layer includes a first contact hole(141) and a second contact hole(142) exposing a source area(152) and a drain area(154) respectively. The first interlayer insulating layer placed on the maintenance electrode wire(133) is thinner than other parts.
摘要翻译：目的：提供一种制造薄膜晶体管阵列基板的方法，以通过在形成接触孔中的维护电极线上略微图案化第一层间绝缘层来最小化寄生电容，从而充分确保维护电容。构成：在形成栅极线（123）和维护电极线（131,133）的栅极绝缘层（140）上形成由具有低介电常数的绝缘材料形成的第一层间绝缘层（801）。第一层间绝缘层包括分别暴露源极区域（152）和漏极区域（154）的第一接触孔（141）和第二接触孔（142）。放置在维护电极线（133）上的第一层间绝缘层比其它部分薄。

13. 发明公开

KR1020030087188A 다수의 반도체 소자를 동시에 성형하는 성형 장비 失效
标题翻译：模具设备同时成型半导体器件的多样性
公开(公告)号：KR1020030087188A
公开(公告)日：2003-11-14
申请号：KR1020020025135
申请日：2002-05-07
申请人： 삼성전자주식회사
发明人： 이성수 , 이대성 , 박경수
IPC分类号： H01L21/56
CPC分类号： B29C45/02 , B29C45/021 , B29C45/14655 , B29C45/768 , B29C2945/76006 , B29C2945/76163 , B29C2945/76943 , H01L2224/45144 , H01L2224/48091 , Y10S425/228 , H01L2924/00014 , H01L2924/00
摘要： PURPOSE: Molding equipment for simultaneously molding a plurality of semiconductor devices is provided to be capable of effectively preventing the mass generation of molding failures by detecting the malfunction of each plunger using a plurality of sensors. CONSTITUTION: The molding equipment for simultaneously molding a plurality of semiconductor devices is provided with a mold(200) and a plurality of plungers(110) inserted in the mold for injecting molding compound in order to encapsulate the semiconductor device. The molding equipment for simultaneously molding a plurality of semiconductor devices further includes a plurality of sensors(600) installed at each plunger for detecting the malfunction of each plunger and a plunger block(100) controlling the motion of the plungers.
摘要翻译：目的：同时成型多个半导体器件的成型设备能够通过使用多个传感器检测每个柱塞的故障来有效地防止成型故障的大量产生。构成：用于同时成型多个半导体器件的成型设备设置有模具（200）和插入到用于注射模塑料的模具中的多个柱塞（110），以封装半导体器件。用于同时成型多个半导体器件的成型设备还包括安装在每个柱塞处的多个传感器（600），用于检测每个柱塞的故障;以及柱塞块（100），其控制柱塞的运动。

14. 发明公开

KR1020030074038A 액정 표시 장치 기판 失效
标题翻译：液晶显示基板
公开(公告)号：KR1020030074038A
公开(公告)日：2003-09-19
申请号：KR1020020021542
申请日：2002-04-19
申请人： 삼성전자주식회사
发明人： 이대성 , 이건종 , 민훈기 , 이원규
IPC分类号： G02F1/1345
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136272 , H01L21/02282
摘要： PURPOSE: A liquid crystal display substrate is provided to minimize a smear caused by an organic layer. CONSTITUTION: A liquid crystal display substrate includes an image display part(D) in which a plurality of signal lines(22,62) for transmitting video signals or scan signals are formed, a pad part(P) having a plurality of pads(24,68) respectively connected to the signal lines, and a fan-out part(O) located between the image display part and pad part. The pad part receives the video signals or scan signals from the outside to transmit the signals to the signal lines. The fan-out part has connectors for connecting the signal lines with the pads respectively. A part of the connectors has at least two portions(A,B) bent at an obtuse angle or curved portions respectively connected to the signal lines. Each of the connectors is composed of at least two different conductive layers.
摘要翻译：目的：提供一种液晶显示基板，以最小化由有机层引起的污迹。构成：液晶显示基板包括图像显示部分（D），其中形成用于传输视频信号或扫描信号的多个信号线（22,62），具有多个焊盘（24）的焊盘部分（P），68）和分别连接到信号线的扇出部分（O）和位于图像显示部分和焊盘部分之间的扇出部分（O）。焊盘部分从外部接收视频信号或扫描信号以将信号发送到信号线。扇出部分具有分别用于将信号线与焊盘连接的连接器。连接器的一部分具有至少两个弯曲成钝角的部分（A，B）或分别连接到信号线的弯曲部分。每个连接器由至少两个不同的导电层组成。

15. 发明公开

KR1020030028100A ＴＢＧＡ 패키지 조립 공정용 컬 분리 장치와 방법 有权
标题翻译：用于在TBGA封装组件工艺中分离CULL的装置和方法
公开(公告)号：KR1020030028100A
公开(公告)日：2003-04-08
申请号：KR1020010060045
申请日：2001-09-27
申请人： 삼성전자주식회사
发明人： 이대성 , 전병철
IPC分类号： H01L21/56
CPC分类号： H01L21/565 , H01L2224/48091 , Y10T29/49146 , Y10T29/49172 , Y10T29/49821 , Y10T29/49822 , Y10T29/53274 , H01L2924/00014
摘要： PURPOSE: An apparatus and method for separating cull in a TBGA(Tape Ball Grid Array) package assembly process are provided to separate the cull generated from a molding process by improving a step coverage between a tape wiring substrate and a carrier frame. CONSTITUTION: A cull separation apparatus(30) includes a cull support block(40), a frame support block(50), a frame holder(60), a pressure portion(70), and a cup holder(80). The cull support block(40) is used for supporting the cull connected with a semifinished product(10). The frame support block(50) is arranged at both sides of the cull support block(40). The frame support block(50) is used for loading the semifinished product(10) adhered to a carrier frame(13). The frame holder(60) is arranged on an upper portion of the frame support block(50) in order to contact and fix the semifinished product(10) to the frame support block(50). The pressing portion(70) is installed at an edge portion of the frame holder(60). A roller(73) is installed at an end portion of the pressing portion(70). The cup holder(80) includes a holder block(81), a vacuum tube(83), and an absorbing pad(85).
摘要翻译：目的：提供一种用于分离TBGA（带状球栅阵列）包装组装过程中的剔除的装置和方法，以通过改善带状布线基板和载体框架之间的台阶覆盖来分离由模制过程产生的剔除。构成：剔除装置（30）包括ull支撑块（40），框架支撑块（50），框架保持器（60），压力部分（70）和杯架（80）。 ull支撑块（40）用于支撑与半成品（10）连接的剔除。框架支撑块（50）布置在ull支撑块（40）的两侧。框架支撑块（50）用于装载粘附到承载框架（13）上的半成品（10）。框架架（60）布置在框架支撑块（50）的上部，以便将半成品（10）接触并固定到框架支撑块（50）。按压部（70）安装在框架保持架（60）的边缘部。辊（73）安装在按压部（70）的端部。杯架（80）包括保持器块（81），真空管（83）和吸收垫（85）。

16. 发明公开

KR1020020039011A 반도체 칩 패키지용 수지 성형 장치 无效
标题翻译：用于半导体芯片封装的树脂模制装置
公开(公告)号：KR1020020039011A
公开(公告)日：2002-05-25
申请号：KR1020000068883
申请日：2000-11-20
申请人： 삼성전자주식회사
发明人： 이대성 , 김병호
IPC分类号： H01L21/56
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： PURPOSE: A resin molding apparatus for a semiconductor chip package is provided to prevent a lead frame from being torn or bent and to prevent a molding defect like a chip-out, by reducing stress applied to the periphery of a guide hole of the lead frame. CONSTITUTION: A molding die(10) includes upper and lower dies(11,12) which have cavities(24,25) for forming an inner space(26) to encapsulate the lead frame(60) by using molding resin wherein a semiconductor chip is mounted on the lead frame. A position determining pin has elasticity for aligning the position of the lead frame, inserted into the guide hole formed in the lead frame of the molding die.
摘要翻译：目的：提供一种用于半导体芯片封装的树脂模制装置，以防止引线框架被撕裂或弯曲，并且通过减少施加到引线框架的引导孔的周边的应力来防止诸如切屑的模制缺陷。构成：成型模具（10）包括具有用于形成内部空间（26）的空腔（24,25）的上模具和下模具（11,12），以通过使用模制树脂封装引线框架（60），其中半导体芯片安装在引线框架上。位置确定销具有弹性，用于对准插入到形成在成型模具的引线框架中的引导孔中的引线框架的位置。

17. 发明公开

KR1020010075957A 반도체 패키지 제조용 몰드 금형장치 无效
标题翻译：用于制造半导体封装的成型装置
公开(公告)号：KR1020010075957A
公开(公告)日：2001-08-11
申请号：KR1020000002912
申请日：2000-01-21
申请人： 삼성전자주식회사
发明人： 이대성 , 이도우 , 이성수
IPC分类号： H01L21/02
摘要： PURPOSE: A molding apparatus for manufacturing a semiconductor package is provided to make a curl block used in molding process compatible for various semiconductor packages. CONSTITUTION: The molding apparatus includes a pair of bottom base block and upper base block(101,102), a pair of bottom cavity blocks(10a) a pair of upper cavity blocks(10b), a pot block(20), and a curl block(30). The pair of bottom base block and upper base block are arranged to face each other and to be coupled with each other according to a pressure condition. The bottom cavity blocks are implemented on both ends of the bottom base blocks to be assembled with the bottom base block in one piece. The upper cavity blocks are implemented on both ends of the upper base blocks to be assembled with the top base block in one piece. The pot block is applied between the bottom cavity blocks and provides EMC(epoxy mold compound material) material to the bottom cavity blocks and the upper cavity blocks. The curl block is applied by the upper cavity blocks and defines the pathway of the EMC material provided to the bottom cavity block and the upper cavity block. The surface corresponding to the port block is a flat type.
摘要翻译：目的：提供一种用于制造半导体封装的成型装置，以使得与各种半导体封装兼容的成型工艺中使用的卷曲块。构成：成型装置包括一对底部底座块和上部基座块（101,102），一对底部空腔块（10a），一对上部空腔块（10b），锅部块（20）和卷曲块（30）。一对底部底座块和上部基座块被布置成相互面对并且根据压力条件彼此联接。底部凹槽块实现在底部基座的两端，以与底部基座块组装成一体。上部空腔块在上部基座的两端上实现，以与顶部基座块组装成一体。盆底部应用于底部空腔块之间，并向底部空腔模块和上部空腔模块提供EMC（环氧模具复合材料）材料。卷曲块由上部空腔块施加，并且限定提供给底部空腔块和上部空腔块的EMC材料的路径。对应于端口块的表面是平面型。

18. 发明公开

KR1020000001844A 반도체 칩 패키지 몰딩 장치 无效
标题翻译：半导体芯片封装成型设备
公开(公告)号：KR1020000001844A
公开(公告)日：2000-01-15
申请号：KR1019980022303
申请日：1998-06-15
申请人： 삼성전자주식회사
发明人： 이대성 , 이도우 , 마영환 , 전용선
IPC分类号： H01L23/28
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PURPOSE: A molding device for a semiconductor chip package is provided to prevent a defective molding such as porous foam and a brisker. CONSTITUTION: The semiconductor chip package molding device(50) comprises; molding metal mold(10) composed of an upper metal mold(11) and a base metal mold(12); a cavity(cavity; 113) formed by the upper metal mold(11) and the base metal mold(12); a lead frame(31) connected by a conducive metal line(32); a runner(14) connected to the cavity(13).
摘要翻译：目的：提供用于半导体芯片封装的成型装置，以防止诸如多孔泡沫和起泡器之类的不良模制。构成：半导体芯片封装成型装置（50）包括：由上金属模具（11）和贱金属模具（12）组成的金属模具（10）; 由所述上金属模具（11）和所述母金属模具（12）形成的空腔（空腔; 113）; 通过导电金属线（32）连接的引线框架（31）; 连接到所述空腔（13）的流道（14）。

19. 发明授权

KR102223970B1 반도체 장치, 레이아웃 시스템 및 스탠다드 셀 라이브러리 有权
公开(公告)号：KR102223970B1
公开(公告)日：2021-03-09
申请号：KR1020150057968
申请日：2015-04-24
申请人： 삼성전자주식회사
发明人： 이대성 , 문대영 , 김민수
IPC分类号： H01L27/02 , G06F30/00 , G06F17/50
摘要： 반도체장치, 레이아웃시스템및 스탠다드셀 라이브러리(standard cell library)가제공된다. 반도체장치는, 기판; 제1 입력신호의반전된전압레벨에게이팅되어제1 노드를풀 업(pull up)시키는제1 트랜지스터; 제2 입력신호의전압레벨에게이팅되어제1 노드를풀 다운(pull down)시키는제2 트랜지스터; 제2 입력신호의반전된전압레벨에게이팅되어제1 노드를풀 업시키는제3 트랜지스터; 제1 입력신호의전압레벨에게이팅되어제1 노드를풀 다운시키는제4 트랜지스터; 제2 입력신호의전압레벨에게이팅되어제2 노드를풀 다운시키는제5 트랜지스터; 제1 입력신호의반전된전압레벨에게이팅되어제2 노드를풀 업시키는제6 트랜지스터; 제1 입력신호의전압레벨에게이팅되어제2 노드를풀 다운시키는제7 트랜지스터및 제2 입력신호의반전된전압레벨에게이팅되어제2 노드를풀 업시키는제8 트랜지스터를포함하고, 제1 트랜지스터의입력단과제4 트랜지스터의입력단은제1 메탈레이어(metal layer)를통해연결되고, 제2 트랜지스터의입력단과제3 트랜지스터의입력단은제2 메탈레이어를통해연결되고, 제5 트랜지스터의입력단과제8 트랜지스터의입력단은제1 메탈레이어를통해연결되고, 제6 트랜지스터의입력단과제7 트랜지스터의입력단은제2 메탈레이어를통해연결되고, 제2 트랜지스터의입력단과제5 트랜지스터의입력단은기판에형성된제1 게이트의일부분을통해연결되고, 제4 트랜지스터의입력단과제7 트랜지스터의입력단은기판에형성된제2 게이트의일부분을통해연결된다.

20. 发明公开

KR1020170115420A 멀티 비트 플립플롭들 审中-实审
标题翻译：多位触发器
公开(公告)号：KR1020170115420A
公开(公告)日：2017-10-17
申请号：KR1020160077548
申请日：2016-06-21
申请人： 삼성전자주식회사
发明人： 윤두석 , 김민수 , 김정희 , 이대성 , 이현 , 임제임스 , 벌진스메튜
IPC分类号： H03K3/037 , G01R31/3185
摘要： 본개시에따른멀티비트플립플롭은스캔입력신호를수신하는단일스캔입력핀, 적어도제1 및제2 데이터입력신호들을각각수신하는복수의데이터입력핀들, 스캔인에이블신호에따라스캔입력신호및 제1 데이터입력신호중 하나를제1 선택신호로선택하고, 제1 선택신호를래치하여제1 출력신호를제공하는제1 스캔플립플롭, 스캔인에이블신호에따라제1 출력신호에대응하는내부신호및 제2 데이터입력신호중 하나를제2 선택신호로선택하고, 제2 선택신호를래치하여제2 출력신호를제공하는제2 스캔플립플롭, 그리고, 제1 및제2 출력신호들을각각출력하는복수의출력핀들을포함하고, 제1 및제2 스캔플립플롭들의스캔패쓰들은서로연결된다.
摘要翻译：多位触发器在根据本发明是用于接收扫描输入信号引脚，至少第一mitje第二数据输入的多个数据输入管脚，用于根据接收的相应信号时，扫描输入信号和所述第一与所述扫描使能信号的单次扫描输入选择数据输入sinhojung第一选择信号中的一个，并且对应于所述第一输出信号以响应该第一扫描触发器的内部，扫描使能信号由锁存第一选择信号信号和以提供第一输出信号第二扫描触发器，用于选择两个数据输入信号中的一个作为第二选择信号并且用于锁存第二选择信号以提供第二输出信号;以及多个输出引脚并且第一和第二扫描触发器的扫描路径彼此连接。

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