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11. 发明申请

US20100237438A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100237438A1
公开(公告)日：2010-09-23
申请号：US12706056
申请日：2010-02-16
申请人： Takafumi IKEDA , Takahito Nakazawa , Hideaki Maekawa , Yuuichi Tatsumi , Toshifumi Minami
发明人： Takafumi IKEDA , Takahito Nakazawa , Hideaki Maekawa , Yuuichi Tatsumi , Toshifumi Minami
IPC分类号： H01L29/06
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.
摘要翻译：半导体器件具有形成在半导体衬底上的电路元件区域和形成为围绕电路元件区域的保护图案。保护图案包括形成在半导体衬底上的第一元件分离区域，形成在半导体衬底上的第二元件分离区域，其宽度小于第一元件分离区域的宽度;第一元素区域，形成在第一元素分离区域和第二元件分离区域，形成在第一元件分离区域上的第一栅极层，形成在第一栅极层上的布线层，形成在布线层上方的钝化层，第二元素区域，形成在第二栅极层上的绝缘膜元件区域和形成在绝缘膜上的第二栅极层，第一元件分离区域，第一元件区域，第二元件分离区域和第二元件区域从电路元件区域的更靠近的方向定位。

12. 发明授权

US07655481B2 Method for manufacturing industrial products and combination of masks for manufacturing the same 失效
标题翻译：制造工业产品的方法和制造掩模的组合
公开(公告)号：US07655481B2
公开(公告)日：2010-02-02
申请号：US11325545
申请日：2006-01-05
申请人： Yuuichi Tatsumi
发明人： Yuuichi Tatsumi
IPC分类号： H01L21/66
CPC分类号： H01L22/22 , G01R31/2853 , H01L22/32 , H01L2224/05553
摘要： A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.
摘要翻译：一种制造工业产品的方法包括：形成中间产品图案，其通过一系列工艺实现工业产品的中间产品的一部分对应于制造工业产品的程序的一部分; 在所述中间产品图案上形成互连变换绝缘体; 在互连变换绝缘体中的无孔采样接触孔，以便露出中间产品图案的一部分以限定取样位置; 描绘互连变换绝缘体上的评估互连，使得每个评估互连可以电连接到中间产品图案的至少一个采样点; 以及通过评估互连测量被检体取样部位之间的电阻，以便检测中间产品图案中的产品缺陷。

13. 发明授权

US5200926A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5200926A
公开(公告)日：1993-04-06
申请号：US722530
申请日：1991-06-27
申请人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
发明人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
IPC分类号： G11C7/10 , G11C7/22 , G11C8/18
CPC分类号： G11C7/1006 , G11C7/22 , G11C8/18
摘要： A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.
摘要翻译：数据传输控制电路连接在读出放大器和输出缓冲电路之间。数据传送控制电路由脉冲信号发生器提供的脉冲信号控制，具有较长的延迟时间，该脉冲信号不由脉冲信号发生器产生，作为噪声消除器进行操作，并防止从其输出错误信号输出缓冲电路。

14. 发明授权

US5138579A Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation 失效
标题翻译：具有在读取操作中防止高电压施加到存储器和虚设单元的传输门的半导体存储器件
公开(公告)号：US5138579A
公开(公告)日：1992-08-11
申请号：US632613
申请日：1990-12-26
申请人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
发明人： Yuuichi Tatsumi , Hidenobu Minagawa , Hiroshi Iwahashi , Masamichi Asano , Mizuho Imai
IPC分类号： G11C7/00 , G11C16/06 , G11C16/28 , G11C17/00
CPC分类号： G11C16/28
摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.
摘要翻译：半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。

15. 发明授权

US5056064A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5056064A
公开(公告)日：1991-10-08
申请号：US568734
申请日：1990-08-17
申请人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
发明人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
IPC分类号： G11C7/10 , G11C7/22 , G11C8/18 , H03K5/1534
CPC分类号： G11C7/1051 , G11C7/1006 , G11C7/22 , G11C8/18 , H03K5/1534
摘要： A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

16. 发明授权

US5010520A Nonvolatile semiconductor memory device with stabilized data write characteristic 失效
标题翻译：具有稳定数据写特性的非易失性半导体存储器件
公开(公告)号：US5010520A
公开(公告)日：1991-04-23
申请号：US224953
申请日：1988-07-27
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
IPC分类号： G11C16/10 , G11C16/24 , G11C16/30 , G11C16/34
CPC分类号： G11C16/34 , G11C16/10 , G11C16/24 , G11C16/30
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

17. 发明授权

US4959816A Semiconductor integrated circuit 失效
公开(公告)号：US4959816A
公开(公告)日：1990-09-25
申请号：US290721
申请日：1988-12-27
申请人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
发明人： Hiroshi Iwahashi , Hideo Kato , Yuuichi Tatsumi
IPC分类号： G11C7/10 , G11C7/22 , G11C8/18 , H03K5/1534
CPC分类号： G11C7/1051 , G11C7/1006 , G11C7/22 , G11C8/18 , H03K5/1534
摘要： A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

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