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    • 12. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US07214580B2
    • 2007-05-08
    • US11000173
    • 2004-12-01
    • Yoshinori KitamuraShigeki Sugimoto
    • Yoshinori KitamuraShigeki Sugimoto
    • H01L21/8238
    • H01L27/11521H01L21/28273H01L27/115H01L27/11524
    • Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    • 公开了一种半导体器件,包括半导体衬底,该半导体衬底包括由隔离沟槽分隔开的第一和第二元件形成区域,形成在第一和第二元件形成区域上的第一和第二下部栅极绝缘膜,形成在第一和第二元件形成区域上的第一和第二浮置栅极 和第二下栅极绝缘膜,隔离绝缘膜,至少形成在所述隔离沟槽中,并且在其上表面上形成有凹部,形成在所述第一和第二浮栅上的上栅极绝缘膜,以及控制栅极线, 与第一和第二浮动栅极相对的相对部分,其中上部栅极绝缘膜被插入,并且位于凹部内部的部分,第一浮动栅极包括与第二浮动栅极相对的侧表面,并且与包括的侧表面完全对准 在第一元件形成区域中并由隔离沟槽限定。
    • 17. 发明授权
    • Digital-signal-processing camera
    • 数字信号处理相机
    • US5371540A
    • 1994-12-06
    • US133786
    • 1993-10-08
    • Akihiro TamuraAtsushi MorimuraYoshinori Kitamura
    • Akihiro TamuraAtsushi MorimuraYoshinori Kitamura
    • H04N5/067H04N5/77H04N5/91H04N5/14
    • H04N5/0675H04N5/77H04N5/91Y10S348/914
    • In the present invention, a drive circuit 12 drives a solid-state image-pickup element 11 in synchronism with a synchronizing signal generated by a synchronizing signal generation circuit 13, and the solid-state image-pickup element 11 issues an output signal prior to an end time of a horizontal blanking period by a time period T.sub.A. This output signal is processed in a digital signal processing circuit 14 and is issued as a picture signal. At that time, the picture signal is delayed from the synchronizing signal by a time period (T.sub.B -T.sub.A) owing to the signal processing, whereas the synchronizing signal is delayed by a delay circuit 15, in which a delay time made by subtracting a time period T.sub.A from a delay time T.sub.B of the digital signal processing circuit 14 is given, and can be issued in a proper timing for a picture signal output of the digital signal processing circuit 14. Further, by incorporating the delay circuit 15 in an LSI which constitutes the digital signal processing circuit 14, a circuit-construction can be minimized and a disturbance, which is given to the picture signal by the synchronizing signal, can be remarkably eliminated.
    • 在本发明中,驱动电路12与由同步信号发生电路13产生的同步信号同步地驱动固态摄像元件11,并且固态摄像元件11在 水平消隐期的结束时间为时间段TA。 该输出信号在数字信号处理电路14中进行处理,作为图像信号发出。 此时,由于信号处理,图像信号从同步信号延迟一段时间(TB-TA),而同步信号被延迟电路15延迟,其中通过减去时间 给出了数字信号处理电路14的延迟时间TB的周期TA,并且可以在数字信号处理电路14的图像信号输出的适当定时发出。另外,通过将延迟电路15并入LSI 构成数字信号处理电路14,可以最小化电路结构,并且可以显着地消除由同步信号给予图像信号的干扰。
    • 20. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20080206976A1
    • 2008-08-28
    • US12106088
    • 2008-04-18
    • Yoshinori KITAMURAShigeki SUGIMOTO
    • Yoshinori KITAMURAShigeki SUGIMOTO
    • H01L21/28
    • H01L27/11521H01L21/28273H01L27/115H01L27/11524
    • Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    • 公开了一种半导体器件,包括半导体衬底,该半导体衬底包括由隔离沟槽分隔开的第一和第二元件形成区域,形成在第一和第二元件形成区域上的第一和第二下部栅极绝缘膜,形成在第一和第二元件形成区域上的第一和第二浮置栅极 和第二下栅极绝缘膜,隔离绝缘膜,至少形成在所述隔离沟槽中,并且在其上表面上形成有凹部,形成在所述第一和第二浮栅上的上栅极绝缘膜,以及控制栅极线, 与第一和第二浮动栅极相对的相对部分,其中上部栅极绝缘膜被插入,并且位于凹部内部的部分,第一浮动栅极包括与第二浮动栅极相对的侧表面,并且与包括的侧表面完全对准 在第一元件形成区域中并由隔离沟槽限定。