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11. 发明申请

US20080128766A1 MOSFET STRUCTURE WITH ULTRA-LOW K SPACER 审中-公开
标题翻译： MOSFET结构与超低K间隔
公开(公告)号：US20080128766A1
公开(公告)日：2008-06-05
申请号：US12030921
申请日：2008-02-14
申请人： Elbert E. Huang , Philip J. Oldiges , Ghavam G. Shahidi , Christy S. Tyberg , Xinlin Wang , Robert L. Wisnieff
发明人： Elbert E. Huang , Philip J. Oldiges , Ghavam G. Shahidi , Christy S. Tyberg , Xinlin Wang , Robert L. Wisnieff
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/4991 , H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure and method of fabricating the structure incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. The multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. Alternatively, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. The multi-layer spacer may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.
摘要翻译： MOSFET结构和制造该结构的方法包括多层侧壁间隔物，以抑制栅极导体和源极/漏极延伸之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET性能。多层侧壁间隔物形成有介电常数等于1的间隙层和可渗透的低K（例如，小于3.5）的电介质层。或者，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二电介质层。多层间隔物也可以具有第三氮化物或氧化物隔离层。该第三间隔层提供增加的结构完整性。

12. 发明申请

US20080023752A1 BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT 审中-公开
标题翻译： BORON DOPED SiGe HALO用于NFET控制短路通道效应
公开(公告)号：US20080023752A1
公开(公告)日：2008-01-31
申请号：US11460766
申请日：2006-07-28
申请人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
发明人： Xiangdong Chen , Yung Fu Chong , Zhijiong Luo , Xinlin Wang , Haining S. Yang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： An n-type field effect transistor (NFET) and methods of forming a halo for an NFET to control the short channel effect are disclosed. One method includes forming a gate over a silicon substrate; recessing the silicon adjacent to the gate; forming a halo by epitaxially growing boron in-situ doped silicon germanium (SiGe) in the recess; and epitaxially growing silicon over the silicon germanium. Alternatively, the halo can be formed by ion implanting boron into an embedded SiGe region within the silicon substrate. The resulting NFET includes a boron doped SiGe halo embedded within the silicon substrate. The embedded SiGe layer may be a relaxed layer without inserting strain in the channel. The high solid solubility of boron in SiGe and low diffusion rate allows formation of a halo that will maintain the sharp profile, which provides better control of the short channel effect and increasing control over NFET threshold voltage roll-off.
摘要翻译：公开了一种n型场效应晶体管（NFET）和用于形成用于NFET的光晕以控制短沟道效应的方法。一种方法包括在硅衬底上形成栅极; 凹陷与栅极相邻的硅; 通过在凹槽中外延生长硼原位掺杂硅锗（SiGe）来形成卤素; 并在硅锗上外延生长硅。或者，可以通过将硼离子注入到硅衬底内的嵌入的SiGe区域中来形成卤素。所得NFET包括嵌入在硅衬底内的硼掺杂SiGe光晕。嵌入的SiGe层可以是松弛层，而不会在通道中插入应变。硼在SiGe中的高固体溶解度和低扩散速率允许形成将保持尖锐轮廓的光晕，这提供了对短通道效应的更好控制并增加了对NFET阈值电压滚降的控制。

13. 发明申请

US20050056937A1 Connection device and method of forming a connection device 失效
标题翻译：连接装置及形成连接装置的方法
公开(公告)号：US20050056937A1
公开(公告)日：2005-03-17
申请号：US10662709
申请日：2003-09-15
申请人： David Frank , Kathryn Guarini , Christopher Murray , Xinlin Wang , Hon-Sum Wong
发明人： David Frank , Kathryn Guarini , Christopher Murray , Xinlin Wang , Hon-Sum Wong
IPC分类号： H01L23/522 , H01L23/525 , H01L23/48
CPC分类号： H01L23/525 , H01L23/5226 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.
摘要翻译：连接装置包括将第一金属层连接到第二金属层的多个可重新配置的通孔。致动元件设置在第一金属层和第二金属层之间。致动元件改变多个可重新配置的通孔的配置，以改变导电状态和非导通状态之间的多个可重新配置的通孔。

14. 发明申请

US20120091506A1 Method and Structure for pFET Junction Profile With SiGe Channel 有权
标题翻译：具有SiGe通道的pFET结型材的方法和结构
公开(公告)号：US20120091506A1
公开(公告)日：2012-04-19
申请号：US12905158
申请日：2010-10-15
申请人： Kern Rim , William K. Henson , Yue Liang , Xinlin Wang
发明人： Kern Rim , William K. Henson , Yue Liang , Xinlin Wang
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： H01L29/1054 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/6659
摘要： A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source region and the drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided in this disclosure by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is thus provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
摘要翻译：提供了包括位于硅锗（SiGe）沟道的表面上的p沟道场效应晶体管（pFET）器件的半导体结构，其中源极区和漏极区的结分布是突然的。在本公开内容中，通过在位于Si衬底之上的SiGe沟道层的正下方形成N或C掺杂的Si层来提供用于pFET器件的突发的源极/漏极结。因此，提供了其中N或C掺杂的Si层（夹在SiGe沟道层和Si衬底之间）对于p型掺杂剂具有与覆盖的SiGe沟道层大致相同的扩散速率的结构。由于N或C掺杂的Si层和上覆的SiGe沟道层对于p型掺杂物具有基本上相同的扩散率，并且因为N或C掺杂的Si层阻碍p型掺杂剂扩散到下面的Si 衬底，可以形成突发的源极/漏极结。

15. 发明授权

US07452761B2 Hybrid SOI-bulk semiconductor transistors 失效
标题翻译：混合SOI体半导体晶体管
公开(公告)号：US07452761B2
公开(公告)日：2008-11-18
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip J. Oldiges , Bruce B. Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

16. 发明申请

US20080176365A1 Method of making double-gated self-aligned finFET having gates of different lengths 失效
标题翻译：制造具有不同长度的栅极的双门控自对准finFET的方法
公开(公告)号：US20080176365A1
公开(公告)日：2008-07-24
申请号：US12077973
申请日：2008-03-24
申请人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
发明人： Huilong Zhu , Bruce B. Doris , Xinlin Wang , Jochen Beintner , Ying Zhang , Philip J. Oldiges
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7855 , H01L29/7856
摘要： A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.
摘要翻译：提供了一种制造门控半导体器件的方法。这种方法可以包括图案化衬底的单晶半导体区域，以在与衬底的主表面平行的横向方向上延伸并且沿至少基本上垂直且至少基本垂直于主表面的方向延伸，半导体区域具有第一侧和第二侧，例如远离第一侧。第一栅极可以形成在第一侧上，第一栅极在横向上具有第一栅极长度。第二栅极可以形成在第二侧上，第二栅极在横向上具有与第一栅极长度不同的第二栅极长度。在一个实施例中，第二栅极长度可以比第一栅极长度短。在一个实施例中，第一栅极可以主要由多晶硅锗组成，第二栅极可以由多晶硅组成。

17. 发明申请

US20060220152A1 MOSFET structure with ultra-low K spacer 失效
标题翻译： MOSFET结构采用超低K隔离
公开(公告)号：US20060220152A1
公开(公告)日：2006-10-05
申请号：US11095373
申请日：2005-03-31
申请人： Elbert Huang , Philip Oldiges , Ghavam Shahidi , Christy Tyberg , Xinlin Wang , Robert Wisnieff
发明人： Elbert Huang , Philip Oldiges , Ghavam Shahidi , Christy Tyberg , Xinlin Wang , Robert Wisnieff
IPC分类号： H01L29/78 , H01L21/469
CPC分类号： H01L29/4991 , H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Disclosed is a MOSFET structure and method of fabricating the structure that incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. In one embodiment, the multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. In another embodiment, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. Either embodiment may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.
摘要翻译：公开了一种MOSFET结构和制造该结构的方法，该结构包括多层侧壁间隔物以抑制栅极导体和源/漏扩展之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET的性能。在一个实施例中，多层侧壁间隔物形成有具有等于1的介电常数的间隙层和可渗透的低K（例如，小于3.5）的电介质层。在另一个实施例中，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二介电层。任一实施例也可以具有第三氮化物或氧化物隔离层。该第三间隔层提供增加的结构完整性。

18. 发明申请

US20060214301A1 Connection device 有权
标题翻译：连接设备
公开(公告)号：US20060214301A1
公开(公告)日：2006-09-28
申请号：US11430477
申请日：2006-05-09
申请人： David Frank , Kathryn Guarini , Christopher Murray , Xinlin Wang , Hon-Sum Wong
发明人： David Frank , Kathryn Guarini , Christopher Murray , Xinlin Wang , Hon-Sum Wong
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/525 , H01L23/5226 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.
摘要翻译：连接装置包括将第一金属层连接到第二金属层的多个可重新配置的通孔。致动元件设置在第一金属层和第二金属层之间。致动元件改变多个可重新配置的通孔的配置，以改变导电状态和非导通状态之间的多个可重新配置的通孔。

19. 发明申请

US20120168864A1 SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE 审中-公开
标题翻译：用于改善短路通道效应控制，对准电容和接头泄漏的自对准井
公开(公告)号：US20120168864A1
公开(公告)日：2012-07-05
申请号：US13418862
申请日：2012-03-13
申请人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
发明人： Robert H. Dennard , Brian J. Greene , Zhibin Ren , Xinlin Wang
IPC分类号： H01L29/772
CPC分类号： H01L29/66772 , H01L21/26586 , H01L21/823814 , H01L29/105 , H01L29/66492 , H01L29/66537 , H01L29/66545 , H01L29/66659 , H01L29/7848 , H01L29/78654 , H01L29/78696
摘要： A transistor device includes a patterned gate structure formed over a substrate, the patterned gate structure including a gate conductor, a gate dielectric layer and sidewall spacers; and a doped well implant formed in the substrate, the well implant being self-aligned with the patterned gate structure.
摘要翻译：晶体管器件包括形成在衬底上的图案化栅极结构，所述图案化栅极结构包括栅极导体，栅极电介质层和侧壁间隔物; 以及形成在衬底中的掺杂阱注入，阱注入与图案化栅极结构自对准。

20. 发明申请

US20110175170A1 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET 失效
标题翻译：用于制造低漏电和低失真的NMOSFET的结构和方法
公开(公告)号：US20110175170A1
公开(公告)日：2011-07-21
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

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