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11. 发明授权

US06207492B1 Common gate and salicide word line process for low cost embedded DRAM devices 有权
标题翻译：用于低成本嵌入式DRAM器件的普通门和自杀字线工艺
公开(公告)号：US06207492B1
公开(公告)日：2001-03-27
申请号：US09587466
申请日：2000-06-05
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873
摘要： A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.
摘要翻译：已经开发了用于在栅极结构上以及重掺杂的源极/漏极区域上形成具有硅化物形状的逻辑器件的过程，同时仅在栅极结构上形成具有硅化物形状的嵌入式DRAM器件。该工艺在嵌入式DRAM器件区域中具有形成在栅极结构之间的空间中的氧化硅阻挡形状。使用高密度等离子体沉积方法形成氧化硅阻挡形状，该方法在嵌入式DRAM器件区域中的栅极结构之间的狭窄空间中沉积厚的氧化硅层，并且在栅极结构中的较宽空间中沉积薄的氧化硅层逻辑器件区域，并在所有栅极结构的顶表面上。然后采用全面的干蚀刻方法从所有栅极结构的顶表面以及逻辑器件区域中的栅极结构之间的空间中移除薄氧化硅层，同时在栅极之间形成期望的氧化硅阻挡形状结构，因此允许仅在栅极结构的顶表面上以及在逻辑器件区域中的重掺杂的源/漏区上形成随后的自对准硅化物形状。

12. 发明授权

US06194234B1 Method to evaluate hemisperical grain (HSG) polysilicon surface 有权
标题翻译：评估半晶粒（HSG）多晶硅表面的方法
公开(公告)号：US06194234B1
公开(公告)日：2001-02-27
申请号：US09324925
申请日：1999-06-04
申请人： Kuo-Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Yu-Hua Lee
发明人： Kuo-Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Yu-Hua Lee
IPC分类号： G01R3126
CPC分类号： H01L22/12
摘要： A new method based on measuring the weight of a wafer (on which the layer of HSG has been deposited) before (W1) and after (W2) the surface of the HSG layer is coated with a layer of either photoresist or SOG. The difference delta W=W2−W1 provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG. This new method can also be based on measuring the weight W of rejected or dropped PR or SOG after the surface of the HSG layer has been coated with a layer of either photoresist or SOG. The weight of the rejected or dropped PR or SOG also provides an indicator of the roughness or smoothness of the surface of the deposited layer of HSG.
摘要翻译：基于测量在HSG层的表面之前（W1）和之后（W2）的晶片（其上沉积了HSG的层）的重量的新方法涂覆有光致抗蚀剂或SOG层。差值ΔW= W2-W1提供HSG沉积层的表面的粗糙度或平滑度的指标。这种新方法也可以基于测量在HSG层的表面已经涂覆有光致抗蚀剂或SOG层之后的被拒绝或掉落的PR或SOG的重量W。拒收或掉落的PR或SOG的重量也提供HSG沉积层的表面的粗糙度或平滑度的指标。

13. 发明授权

US6162686A Method for forming a fuse in integrated circuit application 有权
标题翻译：集成电路应用中形成保险丝的方法
公开(公告)号：US6162686A
公开(公告)日：2000-12-19
申请号：US156362
申请日：1998-09-18
申请人： Kuo Ching Huang , Tse-Liang Ying , Yu-Hua Lee , Ming-Hsin Li
发明人： Kuo Ching Huang , Tse-Liang Ying , Yu-Hua Lee , Ming-Hsin Li
IPC分类号： H01L23/525 , H01L21/336 , H01L21/00 , H01L21/331 , H01L21/44 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a grooved fuse (plug fuse) in the same step that via plugs are formed in the guard ring area 14 and in product device areas. A key point of the invention is to form fuses from the via plug layer, not from the metal layers. Also, key guard rings are formed around the plug guise. The invention can include the following: a semiconductor structure is provided having a fuse area, a guard ring area surrounding the fuse area; and a device area. First and second conductive strips are formed. First and second insulating layers are formed over the first and second conductive strips. Plug contacts and fuse plugs are formed through the first and second insulating layers to the first and second conductive strips. A third insulating layer is formed over the second insulating layer. Metal lines are formed over the third insulating layer in the device area. A fuse via opening is formed in the third insulating layer. A plug fuse is formed in the fuse via opening. A fourth insulating layer is formed over the plug fuse and the third insulating layer. A fuse opening is formed at least partially though the fourth insulating layer over the fuse area.
摘要翻译：在通过塞子形成在保护环区域14和产品装置区域中的相同步骤中形成带槽保险丝（插头保险丝）的方法。本发明的一个关键点是从通孔塞层而不是金属层形成保险丝。此外，围绕插头形状形成关键保护环。本发明可以包括：提供具有保险丝区域的半导体结构，围绕保险丝区域的保护环区域; 和设备区域。形成第一和第二导电条。第一和第二绝缘层形成在第一和第二导电条上。插头触点和熔丝插头通过第一和第二绝缘层形成到第一和第二导电条。在第二绝缘层上形成第三绝缘层。金属线形成在器件区域中的第三绝缘层上。在第三绝缘层中形成保险丝通孔。保险丝通过开口形成插头保险丝。在插头熔断器和第三绝缘层上形成第四绝缘层。保险丝开口至少部分地通过保险丝区域上的第四绝缘层形成。

14. 发明授权

US06373369B2 High efficiency thin film inductor 有权
标题翻译：高效薄膜电感
公开(公告)号：US06373369B2
公开(公告)日：2002-04-16
申请号：US09839927
申请日：2001-04-23
申请人： Kuo-Ching Huang , Jin-Yuan Lee , Tse-Liang Ying
发明人： Kuo-Ching Huang , Jin-Yuan Lee , Tse-Liang Ying
IPC分类号： H01F500
CPC分类号： H01F5/003
摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.
摘要翻译：描述了改进的薄膜电感器设计。使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。如果使用介电铁磁材料，则从设计中去除该约束。示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

15. 发明授权

US06287939B1 Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation 有权
标题翻译：用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法
公开(公告)号：US06287939B1
公开(公告)日：2001-09-11
申请号：US09216789
申请日：1998-12-21
申请人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang
发明人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76895
摘要： The invention provides a method for fabricating a shallow trench isolation which is not susceptable to buried contact trench formation. The invention also provides immunity from the STI “kink effect,” as well as benefits associated with nitridation. The process begins by forming a pad oxide layer on a semiconductor substrate. A nitride layer is formed on the pad oxide layer. The nitride layer, the pad oxide layer, and the semiconductor substrate are patterned to form trenches. Next, a fill oxide layer is formed over the nitride layer, the pad oxide layer, and the semiconductor substrate. The fill oxide layer is chemical-mechanical polished, stopping on the nitride layer to form fill oxide regions. N2 ions are implanted into the fill oxide regions. An anneal is performed to form a buried oxynitride layer. The buried oxynitride layer is partially above the level of the top surface of the semiconductor substrate and partially below the level of the top surface of the semiconductor substrate. The nitride layer is removed. Then, the pad oxide layer and portions of the fill oxide regions are removed using the buried oxynitride layer as an etch stop, forming shallow trench isolations.
摘要翻译：本发明提供一种用于制造不易于埋入接触沟槽形成的浅沟槽隔离的方法。本发明还提供了对STI“扭结效应”的免疫力以及与氮化相关的益处。该过程开始于在半导体衬底上形成衬垫氧化物层。在衬垫氧化物层上形成氮化物层。图案化氮化物层，衬垫氧化物层和半导体衬底以形成沟槽。接下来，在氮化物层，衬垫氧化物层和半导体衬底之上形成填充氧化物层。填充氧化物层进行化学机械抛光，在氮化物层上停止形成填充氧化物区域。将N 2离子注入填充氧化物区域。进行退火以形成掩埋的氮氧化物层。掩埋的氧氮化物层部分地高于半导体衬底的顶表面的高度，并且部分地低于半导体衬底的顶表面的水平。去除氮化物层。然后，使用掩埋氧氮化物层作为蚀刻停止层，去除衬垫氧化物层和填充氧化物区域的部分，形成浅沟槽隔离。

16. 发明授权

US06214715B1 Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition 有权
标题翻译：用于制造自对准接触的方法，其消除使用两步间隔物沉积的键孔问题
公开(公告)号：US06214715B1
公开(公告)日：2001-04-10
申请号：US09349841
申请日：1999-07-08
申请人： Kuo-Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang
发明人： Kuo-Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang
IPC分类号： H01L2144
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10885 , H01L28/91 , H01L28/92
摘要： This invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a device layer, a first inter poly oxide layer (IPO-1), and a conductive structure (such as a bit line) thereover, and having a contact area on the device layer adjacent to the conductive structure. The semiconductor structure can further include an optional etch stop layer overlying the first inter poly oxide layer. The conductive structure comprises at least one conductive layer with a hard mask thereover. A first spacer layer is formed over the hard mask and the IPO-1 layer and anisotropically etched to form first sidewall spacers on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask such that the profile of the first sidewall spacers are not concave at any point. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer is formed over the second sidewall spacers, the hard mask, and the IPO-1 layer, whereby the second inter poly oxide layer is free from key holes. A contact opening is formed in the second inter poly oxide layer and the first inter poly oxide layer over the contact area. A contact plug is formed in the contact openings.
摘要翻译：本发明提供一种用于使用两步侧壁间隔物沉积形成无键孔的自对准接触的方法。该过程开始于提供具有器件层，第一多晶硅氧化物层（IPO-1）和导电结构（例如位线）的半导体结构，并且在与其相邻的器件层上具有接触区域导电结构。半导体结构还可以包括覆盖在第一多晶硅氧化物层上的任选的蚀刻停止层。导电结构包括至少一个具有硬掩模的导电层。在硬掩模和IPO-1层上形成第一间隔层，并且各向异性蚀刻以在导电结构的侧壁上形成直到硬掩模的底部以上的水平并且低于硬掩模，使得第一侧壁隔片的轮廓在任何点都不是凹的。第二间隔层形成在第一侧壁间隔物上并且各向异性蚀刻以形成第二侧壁间隔物，其具有在任何点处不凹的轮廓。在第二侧壁间隔物，硬掩模和IPO-1层上形成第二多晶硅氧化物层，由此第二多晶氧化物层没有键孔。在接触区域上的第二多晶氧化物层和第一多晶氧化物层中形成接触开口。在接触开口中形成接触塞。

17. 发明授权

US6080637A Shallow trench isolation technology to eliminate a kink effect 有权
标题翻译：浅沟槽隔离技术消除扭结效应
公开(公告)号：US6080637A
公开(公告)日：2000-06-27
申请号：US206736
申请日：1998-12-07
申请人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Yeh Shih
发明人： Kuo Ching Huang , Tse-Liang Ying , Wen-Chuan Chiang , Cheng-Yeh Shih
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A process for creating an insulator filled, shallow trench, in a semiconductor substrate, in which the insulator layer in the shallow trench, is not exposed to procedures used to remove defining composite insulator layers, has been developed. The process features creating a lateral recess, in a thick silicon nitride layer, used as a component of a composite insulator layer, where the composite insulator layer is used for subsequent definition of the shallow trench, in the semiconductor substrate. An insulator deposition, filling openings, and recesses, in the composite insulator layer, and filling the shallow trench, followed by removal of excess insulator fill, on the top surface of the composite insulator layer, results in the formation of a "T" shape insulator, comprised of an insulator shape, in the shallow trench, and comprised of a wider insulator shape, located in the composite insulator shape, with the lateral recess in the thick silicon nitride layer, and with the wider insulator shape, overlying the narrow, insulator shape, in the shallow trench. The insulator, in the shallow trench, is protected from the procedure used to remove components of the composite insulator layer, by the wider insulator shape.
摘要翻译：已经开发了在半导体衬底中形成绝缘体填充的浅沟槽的方法，其中浅沟槽中的绝缘体层不暴露于用于移除限定复合绝缘体层的程序。该工艺的特征是在半导体衬底中产生在厚氮化硅层中用作复合绝缘体层的组分的横向凹槽，其中复合绝缘体层用于随后定义浅沟槽。在复合绝缘体层中的绝缘体沉积，填充开口和凹陷，以及填充浅沟槽，然后在复合绝缘体层的顶表面上除去多余的绝缘体填充物，导致形成“T”形绝缘体，由绝缘体形状构成，位于浅沟槽中，并且由更宽的绝缘体形状组成，位于复合绝缘体形状中，侧壁凹陷在厚氮化硅层中，并且具有更宽的绝缘体形状，绝缘体形状，在浅沟槽。通过更宽的绝缘体形状，在浅沟槽中的绝缘体被保护以避免用于去除复合绝缘体层的部件的程序。

18. 发明授权

US5946596A Method for preventing polycide line deformation by polycide hardening 失效
标题翻译：通过多硅化物硬化防止多杀线变形的方法
公开(公告)号：US5946596A
公开(公告)日：1999-08-31
申请号：US734624
申请日：1996-10-18
申请人： Tse-Liang Ying
发明人： Tse-Liang Ying
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/44
CPC分类号： H01L21/32053 , H01L21/76819
摘要： The present invention provides a method for preventing a polycide line situated between two dielectric layers from deformation during a reflow process for one of the dielectric layers by annealing the polycide line and thereby increasing its hardness prior to the reflow process being conducted. The annealing process can be carried out either before or after the polycide line is formed at an annealing temperature in the range between about 700.degree. C. and about 1000.degree. C. in a furnace or by a rapid thermal process.
摘要翻译：本发明提供了一种防止位于两个电介质层之间的多硅化物线在电介质层的回流工艺期间通过退火多孔线而变形，从而在进行回流工艺之前增加其硬度的方法。在退火温度范围为700〜1000℃的快速热处理之前或之后，可以进行退火处理。

19. 发明授权

US06433665B1 High efficiency thin film inductor 有权
公开(公告)号：US06433665B1
公开(公告)日：2002-08-13
申请号：US09839702
申请日：2001-04-23
申请人： Kuo-Ching Huang , Jin Yuan Lee , Tse-Liang Ying
发明人： Kuo-Ching Huang , Jin Yuan Lee , Tse-Liang Ying
IPC分类号： H01F500
摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

20. 发明授权

US06278352B1 High efficiency thin film inductor 有权
标题翻译：高效薄膜电感
公开(公告)号：US06278352B1
公开(公告)日：2001-08-21
申请号：US09359892
申请日：1999-07-26
申请人： Kuo-Ching Huang , Jin-Yuan Lee , Tse-Liang Ying
发明人： Kuo-Ching Huang , Jin-Yuan Lee , Tse-Liang Ying
IPC分类号： H01F500
CPC分类号： H01F5/003
摘要： An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.
摘要翻译：描述了改进的薄膜电感器设计。使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。如果使用介电铁磁材料，则从设计中去除该约束。示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

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