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    • 11. 发明授权
      US06340611B1 Nonvolatile semiconductor memory device 有权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US06340611B1
    • 2002-01-22
    • US09628278
    • 2000-07-28
    • Kazuhiro Shimizu , Seiichi Aritome , Toshiharu Watanabe , Kazuhito Narita
    • Kazuhiro Shimizu , Seiichi Aritome , Toshiharu Watanabe , Kazuhito Narita
    • H01L218238
    • H01L27/11521 , H01L27/115 , H01L27/11524
    • A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.
    • 非易失性半导体存储器件包括半导体衬底，设置在半导体衬底中的元件隔离区，由元件隔离区中的两个相邻元件隔离区限定的第一元件区和形成在元件区中的存储单元晶体管， 的存储单元晶体管包括形成在对应的一个元件隔离区域上的第一栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极，形成在浮置栅电极上的第二栅极绝缘膜和形成的控制电极 在第二栅极绝缘膜上并且共同连接到特定数量的存储单元晶体管中以用作字线，并且浮置栅极包括第一导电构件，其侧面与两个相邻侧的端部接触 和与第一导电膜电连接的第二导电部件 并且形成为跨越两个相邻的元件隔离区域之间的间隙。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 12. 发明授权
      US6157056A Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays 失效
    • Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays
    • 半导体存储器件具有构成存储单元阵列的多个存储单元晶体管
    • US6157056A
    • 2000-12-05
    • US8627
    • 1998-01-16
    • Yuji Takeuchi , Toshiharu Watanabe , Seiichi Aritome , Hiroshi Watanabe , Kazuhiro Shimizu
    • Yuji Takeuchi , Toshiharu Watanabe , Seiichi Aritome , Hiroshi Watanabe , Kazuhiro Shimizu
    • G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/708 , H01L21/336
    • H01L27/115
    • The semiconductor memory device comprises first and second memory cell rows each constructed by connecting a plurality of memory cell transistors, and third and fourth memory cell rows which are provided to be respectively adjacent to the first and second memory cell rows, such that element separation regions are respectively provided between adjacent memory cell rows. First and second transistors are connected between a drain or a source of the first memory cell row and a drain or a source of the second memory cell row. Gate electrodes of the first and third transistors are connected by a first gate line, and gate electrodes of the second and fourth transistors are connected by a second gate line. The first and second transistors are connected to a data line by a first contact. The third and fourth transistors are connected to a data line by a second contact. A first spacing element is connected between the first and second transistors and a second spacing element is connected between the third and fourth transistors, so that the distance between the first and second contacts is widened. The first contact is provided between the first transistor and the first spacing element. The second contact is provided between the fourth transistor and the second spacing element. The first spacing element is connected through the third gate line to the second spacing element.
    • 半导体存储器件包括通过连接多个存储单元晶体管构成的第一和第二存储单元行，以及分别设置成分别与第一和第二存储单元行相邻的第三和第四存储单元行，使得元件分离区 分别设置在相邻的存储单元行之间。 第一和第二晶体管连接在第一存储单元行的漏极或源极与第二存储单元行的漏极或源极之间。 第一和第三晶体管的栅极通过第一栅极线连接，第二和第四晶体管的栅电极通过第二栅极线连接。 第一和第二晶体管通过第一接触连接到数据线。 第三和第四晶体管通过第二接触连接到数据线。 第一间隔元件连接在第一和第二晶体管之间，第二间隔元件连接在第三和第四晶体管之间，使得第一和第二触点之间的距离变宽。 第一触点设置在第一晶体管和第一间隔元件之间。 第二触点设置在第四晶体管和第二间隔元件之间。 第一间隔元件通过第三栅极线连接到第二间隔元件。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 16. 发明授权
      US4975754A Trench dual-gate MOSFET 失效
    • Trench dual-gate MOSFET
    • 沟槽双栅极MOSFET
    • US4975754A
    • 1990-12-04
    • US373059
    • 1989-06-29
    • Hidemi Ishiuchi , Toshiharu Watanabe , Kinuyo Tanaka
    • Hidemi Ishiuchi , Toshiharu Watanabe , Kinuyo Tanaka
    • H01L29/78
    • H01L29/7827 , H01L29/7831
    • A trench dual-gate MOSFET comprises a projection which is bent to enclose a predetermined region on a semiconductor substrate of a first conductivity type. This projection is defined by a trench formed by selectively removing the surface region of the semiconductor substrate. A gate insulation film is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection. A gate electrode is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection, with the gate insulation film interposed and in a manner to surround the projection. A first impurity region of a second conductivity type, which serves as either a source or drain region, is formed in the top portion of the projection. A second impurity region of the second conductivity, which serves as either a drain or source region, is formed in the surface region of that portion of the semiconductor substrate which is located around the base of the projection.
    • 沟槽双栅极MOSFET包括弯曲以包围第一导电类型的半导体衬底上的预定区域的突起。 该突起由通过选择性地去除半导体衬底的表面区域形成的沟槽限定。 在突起的侧壁和位于突起的基部周围的半导体基板部分上形成栅极绝缘膜。 在突起的侧壁和位于突起的基部周围的半导体基板部分上形成有栅电极，栅极绝缘膜以介于突起的方式插入。 在突起的顶部形成有用作源极或漏极区域的第二导电类型的第一杂质区域。 第二导电性的第二杂质区域，其用作漏极或源极区域，形成在半导体衬底的位于突起的基部周围的部分的表面区域中。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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