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11. 发明申请

US20100326067A1 SELF-PROPELLED MACHINE 审中-公开
标题翻译：自动机
公开(公告)号：US20100326067A1
公开(公告)日：2010-12-30
申请号：US12821925
申请日：2010-06-23
申请人： Ralf Weiser , Tobias Noll , Andreas Letz , Martin Buschmann
发明人： Ralf Weiser , Tobias Noll , Andreas Letz , Martin Buschmann
IPC分类号： F16D33/00 , F16D31/02
CPC分类号： F01P7/044 , E01C19/48 , E02F9/226 , F15B21/042
摘要： In a self-propelled machine F for processing paving material, the machine having a liquid cooled combustion engine M and at least one hydraulic circuit H containing hydraulic pumps 6, hydromotors or hydrostatic drive units 7-10 and at least one hydraulic medium reservoir 12, a fan assisted cooling device K including cooling regions 1b, 1c at least for the cooling liquid of the combustion engine M and of the hydraulic medium of the hydraulic circuit H. A hydraulic medium operation temperature setting and regulating device R is provided for the hydraulic medium cooling region 1c constituted by a separate cooler 24 in order to generate an operation temperature T of the hydraulic medium above at least about 60° C. and to maintain this operation temperature depending on the hydraulic load situation in the hydraulic liquid H and on the surrounding climate, independently from a cooling regulating system S for the combustion engine M.
摘要翻译：在用于处理铺路材料的自走机器F中，机器具有液体冷却内燃机M和至少一个包含液压泵6，液压马达或静液压驱动单元7-10和至少一个液压介质储存器12的液压回路H，一个风扇辅助冷却装置K，其至少包括用于内燃机M的冷却液和液压回路H的液压介质的冷却区域1b，1c。液压介质操作温度设定和调节装置R设置在液压介质冷却区域1c由单独的冷却器24构成，以便产生至少约60℃的液压介质的操作温度T，并且根据液压液体H和周围的液压负载情况来保持该操作温度气候，独立于用于内燃机M的冷却调节系统S.

12. 发明授权

US4841469A Matrix times matrix multiplier 失效
标题翻译：矩阵乘矩阵乘数
公开(公告)号：US4841469A
公开(公告)日：1989-06-20
申请号：US222937
申请日：1988-07-22
申请人： Ronald Kuenemund , Tobias Noll
发明人： Ronald Kuenemund , Tobias Noll
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： A circuit for the multiplication of the elements of a multiplicand matrix represented by first digital signals by the elements of a multiplier matrix represented by second digital signals. A multiplicand line is provided for every row of the multiplicand matrix and the individual sections (L11. . . L14) o f these multiplicand lines are connected to bit-associated circuits (bit planes) (BP1. . . BP4). Every bit plane contains the partial product stages (1, 2, 3) which are allocated to the bits of the second digital signals having a defined significance, and also contain an iterative circuit composed of adders (4, 5) and time delay elements (6, 7, 8) in an alternating arrangement.
摘要翻译：用于乘以由第二数字信号表示的乘法器矩阵的元素由第一数字信号表示的乘法矩阵的元素相乘的电路。为被乘数矩阵的每一行提供被乘数线，并且将这些被乘数线连接到位相关电路（位平面）（BP1 ... BP4）的各个部分（L11 ... L14）。每个位平面包含分配给具有确定重要性的第二数字信号的位的部分积级（1,2,3），并且还包含由加法器（4,5）和时间延迟元件（4）组成的迭代电路 6,7,8）。

13. 发明授权

US4748583A Cell-structured digital multiplier of semi-systolic construction 失效
标题翻译：半收缩期建设的细胞结构数字乘法器
公开(公告)号：US4748583A
公开(公告)日：1988-05-31
申请号：US762444
申请日：1985-08-05
申请人： Tobias Noll
发明人： Tobias Noll
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52 , G06F7/527
CPC分类号： G06F7/5312 , G06F2207/388 , G06F2207/3884
摘要： A digital multiplier which has cells arranged in a plurality of rows and columns wherein the rows are assigned to different groups of partial product bits. Sum paths and carry paths are provided which connect the individual cells to each other and at their ends emit signals from which the product bits are formed. The multiplicand bits are stored intermediately together with the sum and carry signals formed in a row and are simultaneously forwarded to the next row in accordance with a pipelining process. It is desired to obtained the least possible delay in feeding a multiplier bit into all the cells of a row so as to achieve short range transit time of the signals between the output of two consecutive rows and this is achieved with a logic link element which is used to form a partial product bit which is contained in a cell which proceeds the row and in which this partial product bit is added to sum signals and carry signals. One of the cells of the following row contains a full adder which is connected to the output of the logic link with a connection line which is provided with a shift register stage. The invention can be used for integrated circuit for digital data processing.
摘要翻译：一种数字乘法器，其具有排列成多个行和列的单元，其中行被分配给不同组的部分乘积位。提供了和路径和携带路径，其将各个单元彼此连接并且在其端部处发射产生乘积位的信号。被乘数位与一行中形成的和和进位信号中间存储，并且根据流水线处理同时转发到下一行。期望获得将乘法器位馈送到行的所有单元中的最小可能的延迟，以便实现两个连续行的输出之间的信号的短距离传播时间，并且这通过逻辑链路元件实现用于形成包含在进行该行的单元中并且将该部分乘积位加到和信号和进位信号的部分乘积位。下一行的单元之一包含一个全加器，它连接到具有移位寄存器级的连接线的逻辑链路的输出。本发明可用于数字数据处理的集成电路。

14. 发明授权

US09222228B2 Road finishing machine and method of operating a road finishing machine 有权
标题翻译：道路整理机及运行道路整理机的方法
公开(公告)号：US09222228B2
公开(公告)日：2015-12-29
申请号：US13196399
申请日：2011-08-02
申请人： Tobias Noll , Ralf Weiser
发明人： Tobias Noll , Ralf Weiser
IPC分类号： E01C19/48
CPC分类号： E01C19/48 , B60W2300/17 , F16D2500/3166 , F16D2500/50883
摘要： In a road finishing machine with a primary power plant and a power transfer to a hydraulic pump and/or a generator for supplying power to hydraulically or electrically operated functional components, the power transfer comprises at least one clutch that can be optionally engaged and disengaged, and a clutch control device is provided by means of which, depending on at least the operator guidance and/or a detected clutch loading situation, a disengagement delay (Δt) automatically overriding the operator guidance can be set, and/or a clutch shifting number restriction can be set by means of a detection interval (dt) moving along in time. The clutch control device actually engages, within the frame of the respective overriding control strategy, the clutch only after the disengagement delay (Δt) has lapsed, if no operation command to the contrary is present, and/or keeps the clutch first engaged, although an operation command to the contrary is present.
摘要翻译：在具有一次发电厂的道路整理机和向液压泵和/或用于向液压或电动操作的功能部件供电的发电机的动力传递中的动力传递包括至少一个可任选地接合和分离的离合器，并且提供离合器控制装置，通过该离合器控制装置，根据至少操作者引导和/或检测到的离合器装载情况，可以设定自动覆盖操作者引导的分离延迟（＆Dgr; t）和/或离合器可以通过沿时间移动的检测间隔（dt）来设定移位数限制。离合器控制装置在相应的超控制策略的框架内实际上仅在分离延迟（＆Dgr; t）已经过去之后接合离合器，如果不存在相反的操作命令，和/或使离合器首先接合虽然存在相反的操作命令。

15. 发明授权

US08517628B2 Road finisher with automatic engine controller 有权
标题翻译：自动发动机控制器的整修机
公开(公告)号：US08517628B2
公开(公告)日：2013-08-27
申请号：US12821970
申请日：2010-06-23
申请人： Ralf Weiser , Tobias Noll , Martin Buschmann , Achim Eul
发明人： Ralf Weiser , Tobias Noll , Martin Buschmann , Achim Eul
IPC分类号： E01C23/07
CPC分类号： E01C19/48
摘要： A self-propelling machine for processing bituminous or concrete pavement material, in particular a road finisher or a feeder. The machine comprises an internal combustion engine as a primary drive source, a controller for the engine, said controller receiving control signals, at least one additional drive unit for functional and operational components of the machine as well as at least one hydraulic circuit comprising a hydraulic medium reservoir. The controller is configured for automatically causing starting and/or stopping of the engine in response to receipt of at least one specific control signal.
摘要翻译：一种用于加工沥青或混凝土路面材料的自走式机器，特别是道路整理机或进料器。该机器包括作为主要驱动源的内燃机，用于发动机的控制器，所述控制器接收控制信号，用于机器的功能和操作部件的至少一个额外的驱动单元以及至少一个液压回路，其包括液压中型水库控制器被配置为响应于接收到至少一个特定控制信号而自动地引起发动机的启动和/或停止。

16. 发明申请

US20120031724A1 ROAD FINISHING MACHINE AND METHOD OF OPERATING A ROAD FINISHING MACHINE 有权
标题翻译：道路修整机及运行道路修整机的方法
公开(公告)号：US20120031724A1
公开(公告)日：2012-02-09
申请号：US13196399
申请日：2011-08-02
申请人： Tobias Noll , Ralf Weiser
发明人： Tobias Noll , Ralf Weiser
IPC分类号： F16D43/00
CPC分类号： E01C19/48 , B60W2300/17 , F16D2500/3166 , F16D2500/50883
摘要： In a road finishing machine with a primary power plant and a power transfer to a hydraulic pump and/or a generator for supplying power to hydraulically or electrically operated functional components, the power transfer comprises at least one clutch that can be optionally engaged and disengaged, and a clutch control device is provided by means of which, depending on at least the operator guidance and/or a detected clutch loading situation, a disengagement delay (Δt) automatically overriding the operator guidance can be set, and/or a clutch shifting number restriction can be set by means of a detection interval (dt) moving along in time. The clutch control device actually engages, within the frame of the respective overriding control strategy, the clutch only after the disengagement delay (Δt) has lapsed, if no operation command to the contrary is present, and/or keeps the clutch first engaged, although an operation command to the contrary is present.
摘要翻译：在具有一次发电厂的道路整理机和向液压泵和/或用于向液压或电动操作的功能部件供电的发电机的动力传递中的动力传递包括至少一个可任选地接合和分离的离合器，并且提供离合器控制装置，通过该离合器控制装置，根据至少操作者引导和/或检测到的离合器装载情况，可以设定自动覆盖操作者引导的分离延迟（＆Dgr; t）和/或离合器可以通过沿时间移动的检测间隔（dt）来设定移位数限制。离合器控制装置在相应的超控制策略的框架内实际上仅在分离延迟（＆Dgr; t）已经过去之后接合离合器，如果不存在相反的操作命令，和/或使离合器首先接合虽然存在相反的操作命令。

17. 发明授权

US06069498A Clock generator for CMOS circuits with dynamic registers 失效
标题翻译：具有动态寄存器的CMOS电路的时钟发生器
公开(公告)号：US06069498A
公开(公告)日：2000-05-30
申请号：US945725
申请日：1997-11-05
申请人： Tobias Noll , Stefan Meier , Matthias Schobinger , Erik De Man
发明人： Tobias Noll , Stefan Meier , Matthias Schobinger , Erik De Man
IPC分类号： G06F1/04 , G11C7/22 , H03K5/151 , H03K5/153 , H03K5/19 , H03K9/06
CPC分类号： H03K5/153 , G11C7/22 , H03K5/19
摘要： An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.
摘要翻译： PCT No.PCT / DE96 / 00794 Sec。 371日期：1997年11月5日 102（e）日期1997年11月5日PCT提交1996年5月7日PCT公布。 WO96 / 36113 PCT出版物日期：1996年11月14日装置具有时钟监视装置，其确定输入时钟信号（PHI 0）的时钟速率是否已经低于预定的最小时钟速率。提供了一种系统，其从输入时钟信号形成主时钟信号（PHI m）和从时钟信号（PHI s），其形式使得动态主机寄存器（ML）的两个开关（S1）并且动态从属寄存器（SL）的开关（S2）关闭，只要时钟速率已经低于最小时钟速率。否则，动态从动锁存器（SL）的动态主锁存器（ML）或开关（S2）中的至少一个开关（S1）关闭。所实现的主要优点是，在输入时钟信号失效的情况下，特别是在具有高流水线流量的电路中，未定义的寄存器状态不会导致不允许的高电流消耗。

18. 发明授权

US5317753A Coordinate rotation digital computer processor (cordic processor) for vector rotations in carry-save architecture 失效
标题翻译：坐标旋转数字计算机处理器（cordic processor），用于进位保存架构中的向量旋转
公开(公告)号：US5317753A
公开(公告)日：1994-05-31
申请号：US667289
申请日：1991-03-11
申请人： Ronald Kuenemund , Tobias Noll
发明人： Ronald Kuenemund , Tobias Noll
IPC分类号： G06F17/16 , G06F7/544
CPC分类号： G06F7/5446
摘要： A CORDIC processor is provided in carry-save architecture in connection with intense pipelining for vector rotations, particularly given problems in real-time processing. The processor comprises a plurality of vector iteration stages and a plurality of angle iteration stages that are partially redundantly present in order to guarantee a convergency of the CORDIC algorithm despite an ambiguity region in the sign detection of carry-save numbers and in order to simplify other circuit components, for example a multiplier. As a result of the carry-save architecture, only incomplete addition/subtraction operations are executed in the iteration stages, and intermediate results in the form of carry and save words are fed through the CORDIC processor on separate line paths until they are added in an adder at the processor output to form the final result vector. The invention is advantageous in the low chip surface requirement that results from a high regularity of the overall structure and from simply-constructed base cells of the vector and angle iteration stages and in the extremely-high processing speed that results from the combination of intense pipelining and the carry-save architecture.
摘要翻译： CORDIC处理器在携带保存架构中提供了与用于向量旋转的强流水线相关联，特别是在实时处理中给定的问题。处理器包括多个矢量迭代阶段和多个角度迭代阶段，其部分冗余存在，以便保证CORDIC算法的可收敛性，尽管在进位保存号码的符号检测中存在模糊区域，并且为了简化其他电路组件，例如乘法器。作为进位保存架构的结果，在迭代阶段仅执行不完全的加法/减法操作，并且以进位和保存字的形式的中间结果通过CORDIC处理器在单独的线路路径上馈送，直到它们被添加到加法器处理器输出以形成最终的结果向量。本发明在低的芯片表面要求方面是有利的，这是由于整体结构的高规整性和简单构建的矢量和角度迭代阶段的基体以及极高的处理速度导致的，和进位保存架构。

19. 发明授权

US4893264A Digital decimation filter 失效
标题翻译：数字抽取滤波器
公开(公告)号：US4893264A
公开(公告)日：1990-01-09
申请号：US224018
申请日：1988-07-25
申请人： Tobias Noll , Stefan Meier
发明人： Tobias Noll , Stefan Meier
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0225 , H03H17/0276 , H03H17/0664 , H03H2017/0692
摘要： A digital decimation filter which includes a multiplexer which receives signal values x.sub.i at a sampling rate of 1/T and where output signals which have half the sampling rate are supplied to two outputs. Separate bit associated circuits BP1 and BP2 are connected to the outputs for each significant figure of the p-place binary filter coefficients c6 through c1 and each of the bit associated circuits include partial products stages Mc6.sub.0 . . . Mc1.sub.0, Mc6.sub.1 . . . Mc1.sub.1 for all of the filter coefficient bits and the bit associated circuits also contain adder-register iterative circuits including delay elements and the output of the iterative circuit of the most significant bit plane BP2 is the output of the filter.
摘要翻译：数字抽取滤波器，其包括以1 / T的采样率接收信号值xi并且具有一半采样率的输出信号被提供给两个输出的多路复用器。分离位相关电路BP1和BP2连接到p位二进制滤波器系数c6至c1的每个有效图的输出，并且每个位相关电路包括部分乘积级Mc60。。。 Mc10，Mc61。。。所有滤波器系数位和位相关电路的Mc11都包含加法寄存器迭代电路，包括延迟元件，最高有效位平面BP2的迭代电路的输出是滤波器的输出。

20. 发明授权

US4888723A Arrangement for bit-parallel addition of binary numbers with carry-save overflow correction 失效
标题翻译：用于进位保存溢出校正的位并行加法二进制数的布置
公开(公告)号：US4888723A
公开(公告)日：1989-12-19
申请号：US60169
申请日：1987-06-10
申请人： Erik De Man , Tobias Noll
发明人： Erik De Man , Tobias Noll
IPC分类号： G06F7/50 , G06F7/508 , G06F7/509
CPC分类号： G06F7/509 , G06F7/4991
摘要： A series of adders (AD.sub.i) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, in case the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by the carry bit thereof. The element AD.sub.kn-1 has the same number of transistors as the other adders AD.sub.0 . . . AD.sub.n-2.
摘要翻译：提供了一系列具有相同意义的二进制数位的输入的加法器（ADi），其输出组合以形成和字的中间和和携带字，用于与二进制补码中的二进制数的位并行加法，节省溢出校正。对于溢出错误的校正，具有第二高有效性的加法器（ADn-2）的进位位被最高有效加法器（ADn-1）的进位位代替，并且在两个最大值的进位位有意义的加法器（ADn-1，ADn-2）不相等，最高有效加法器（ADn-1）的中间和位由其进位位代替。元件ADkn-1具有与其他加法器AD0相同数量的晶体管。。。 ADn-2。

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