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    • 1. 发明授权
    • Coordinate rotation digital computer processor (cordic processor) for
vector rotations in carry-save architecture
    • 坐标旋转数字计算机处理器(cordic processor),用于进位保存架构中的向量旋转
    • US5317753A
    • 1994-05-31
    • US667289
    • 1991-03-11
    • Ronald KuenemundTobias Noll
    • Ronald KuenemundTobias Noll
    • G06F17/16G06F7/544
    • G06F7/5446
    • A CORDIC processor is provided in carry-save architecture in connection with intense pipelining for vector rotations, particularly given problems in real-time processing. The processor comprises a plurality of vector iteration stages and a plurality of angle iteration stages that are partially redundantly present in order to guarantee a convergency of the CORDIC algorithm despite an ambiguity region in the sign detection of carry-save numbers and in order to simplify other circuit components, for example a multiplier. As a result of the carry-save architecture, only incomplete addition/subtraction operations are executed in the iteration stages, and intermediate results in the form of carry and save words are fed through the CORDIC processor on separate line paths until they are added in an adder at the processor output to form the final result vector. The invention is advantageous in the low chip surface requirement that results from a high regularity of the overall structure and from simply-constructed base cells of the vector and angle iteration stages and in the extremely-high processing speed that results from the combination of intense pipelining and the carry-save architecture.
    • CORDIC处理器在携带保存架构中提供了与用于向量旋转的强流水线相关联,特别是在实时处理中给定的问题。 处理器包括多个矢量迭代阶段和多个角度迭代阶段,其部分冗余存在,以便保证CORDIC算法的可收敛性,尽管在进位保存号码的符号检测中存在模糊区域,并且为了简化其他 电路组件,例如乘法器。 作为进位保存架构的结果,在迭代阶段仅执行不完全的加法/减法操作,并且以进位和保存字的形式的中间结果通过CORDIC处理器在单独的线路路径上馈送,直到它们被添加到 加法器处理器输出以形成最终的结果向量。 本发明在低的芯片表面要求方面是有利的,这是由于整体结构的高规整性和简单构建的矢量和角度迭代阶段的基体以及极高的处理速度导致的, 和进位保存架构。
    • 2. 发明授权
    • Matrix times matrix multiplier
    • 矩阵乘矩阵乘数
    • US4841469A
    • 1989-06-20
    • US222937
    • 1988-07-22
    • Ronald KuenemundTobias Noll
    • Ronald KuenemundTobias Noll
    • G06F17/16
    • G06F17/16
    • A circuit for the multiplication of the elements of a multiplicand matrix represented by first digital signals by the elements of a multiplier matrix represented by second digital signals. A multiplicand line is provided for every row of the multiplicand matrix and the individual sections (L11. . . L14) o f these multiplicand lines are connected to bit-associated circuits (bit planes) (BP1. . . BP4). Every bit plane contains the partial product stages (1, 2, 3) which are allocated to the bits of the second digital signals having a defined significance, and also contain an iterative circuit composed of adders (4, 5) and time delay elements (6, 7, 8) in an alternating arrangement.
    • 用于乘以由第二数字信号表示的乘法器矩阵的元素由第一数字信号表示的乘法矩阵的元素相乘的电路。 为被乘数矩阵的每一行提供被乘数线,并且将这些被乘数线连接到位相关电路(位平面)(BP1 ... BP4)的各个部分(L11 ... L14)。 每个位平面包含分配给具有确定重要性的第二数字信号的位的部分积级(1,2,3),并且还包含由加法器(4,5)和时间延迟元件(4)组成的迭代电路 6,7,8)。