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11. 发明申请

US20060134843A1 MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness 失效
标题翻译：具有体接触的SOI衬底上的MOS晶体管和具有可变厚度的栅极绝缘膜
公开(公告)号：US20060134843A1
公开(公告)日：2006-06-22
申请号：US11317687
申请日：2005-12-27
申请人： Shigenobu Maeda , Takuji Matsumoto , Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Shigenobu Maeda , Takuji Matsumoto , Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7841 , H01L29/78615 , H01L29/78654 , Y10S438/981
摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
摘要翻译：本发明的目的是提供一种能够进行身体固定并实现快速且稳定的操作的SOI装置。在栅极（12）的栅极接触焊盘（GP）与SOI层（3）之间的部分之间设置厚度为1〜5nm的栅极绝缘膜（11）和栅极绝缘膜（在栅极接触焊盘（GP）和SOI层（3）之间设置有厚度为5〜15nm的光栅（110）。连续设置栅极绝缘膜（11）和栅极绝缘膜（110）。

12. 发明申请

US20050275021A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050275021A1
公开(公告)日：2005-12-15
申请号：US11197397
申请日：2005-08-05
申请人： Takuji Matsumoto , Takashi Ipposhi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Takuji Matsumoto , Takashi Ipposhi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66545 , H01L21/28052 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7845
摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
摘要翻译：提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的上表面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原的隔离击穿电压。此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

13. 发明申请

US20050253219A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20050253219A1
公开(公告)日：2005-11-17
申请号：US11156554
申请日：2005-06-21
申请人： Takuji Matsumoto , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Takuji Matsumoto , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L21/76 , H01L21/314 , H01L21/318 , H01L21/762 , H01L21/768 , H01L21/8238 , H01L21/84 , H01L23/522 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L29/94 , H01L21/336
CPC分类号： H01L21/76264 , H01L21/3143 , H01L21/3185 , H01L21/76283 , H01L21/84
摘要： A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

14. 发明申请

US20050148089A1 Method for quantitatively determining a reducing substance and a reagent for quantitative determination 有权
标题翻译：用于定量测定还原物质和定量测定试剂的方法
公开(公告)号：US20050148089A1
公开(公告)日：2005-07-07
申请号：US10743741
申请日：2003-12-24
申请人： Masahiro Sekiguchi , Takuji Matsumoto , Hiroyuki Ebinuma
发明人： Masahiro Sekiguchi , Takuji Matsumoto , Hiroyuki Ebinuma
IPC分类号： G01N31/22
CPC分类号： G01N31/22 , Y10T436/18 , Y10T436/182
摘要： The present invention provides a method for quantitatively determining a reducing substance, which comprises reacting a reducing substance in a test specimen with iron (III) ions, reacting iron (II) ions formed by reduction of the iron (III) ions or residual iron (III) ions with a metal indicator which is capable of reacting specifically with the iron (II) ions or the residual iron (III) ions to undergo color development, and carrying out quantitative determination by measuring the degree of color development, wherein a chelating agent which is specific to copper ions is added to the test specimen before the reaction of the reducing substance with the iron (III) ions; and a reagent used for it.
摘要翻译：本发明提供了一种定量测定还原物质的方法，该方法包括使试样中的还原物质与铁（III）离子反应，通过还原铁（III）离子或残余铁形成的铁（II） III）离子与能够与铁（II）离子或残留铁（III）离子特异性反应的金属指示剂进行显色，并通过测量显色程度进行定量测定，其中螯合剂在还原物质与铁（III）离子反应之前，将铜离子特异性添加到试样中; 和用于它的试剂。

15. 发明授权

US06864534B2 Semiconductor wafer 有权
标题翻译：半导体晶圆
公开(公告)号：US06864534B2
公开(公告)日：2005-03-08
申请号：US09930202
申请日：2001-08-16
申请人： Takashi Ipposhi , Takuji Matsumoto
发明人： Takashi Ipposhi , Takuji Matsumoto
IPC分类号： H01L27/12 , H01L21/02 , H01L21/336 , H01L21/762 , H01L23/544 , H01L29/04 , H01L29/786 , H01L27/01 , H01L29/00
CPC分类号： H01L23/544 , H01L21/76254 , H01L29/045 , H01L2223/54406 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation of the wafer for the device formation and the crystal orientation of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).
摘要翻译：为了提供具有用于支撑基板的晶片的晶体取向和用于器件形成的晶片彼此偏移的半导体晶片，其中将提供具有不同晶体取向的两种晶片（其中将提供缺口或取向平面）不是需要准备将具有以相同晶体取向<110>提供的凹口或取向平面的两个半导体晶片中的一个设置为用于支撑衬底的晶片（1），另一个被设置为用于器件形成的晶片。两个晶片与凹槽或取向平面彼此偏移（例如，用于器件形成的晶片的晶体取向<100>和用于支撑衬底的晶片（1）的晶体取向<110>被结合朝同一个方向）。用于器件形成的晶片被分割以获得SOI层（3）。在SOI层（3）上形成MOS晶体管（TR1）等。

16. 发明授权

US06841400B2 Method of manufacturing semiconductor device having trench isolation 失效
标题翻译：制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US06841400B2
公开(公告)日：2005-01-11
申请号：US10216363
申请日：2002-08-12
申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
发明人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
IPC分类号： H01L21/66 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L21/8244 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/10 , H01L27/11 , H01L27/12 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
摘要翻译：本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。在图案化氮化膜（22）之后，测量SOI层3的厚度（S2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S3）。为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。使用所确定的蚀刻条件，并且通过使用图案化氮化物膜22作为蚀刻掩模形成沟槽TR2（S4）。

17. 发明授权

US06713804B2 TFT with a negative substrate bias that decreases in time 失效
标题翻译：具有负的衬底偏置的TFT在时间上减小
公开(公告)号：US06713804B2
公开(公告)日：2004-03-30
申请号：US10199173
申请日：2002-07-22
申请人： Yuuichi Hirano , Takuji Matsumoto , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Takuji Matsumoto , Yasuo Yamaguchi
IPC分类号： H01L27108
CPC分类号： H01L29/78648 , H01L27/1203 , H01L29/78615 , Y10S257/901
摘要： A voltage applying section (32) is connected to a silicon substrate (1). Emission of radiation to a semiconductor device causes a large number of holes to accumulate within a BOX layer (2) in the vicinity of the interface with respect to a silicon layer (3). The amount of accumulation of holes increases with a lapse of time. A voltage applying section (32) applies a negative voltage which decreases with the lapse of time to the silicon substrate (1) in order to cancel out a positive electric field resulting from the accumulated holes. The voltage applying section (32) includes a time counter (30) for detecting the lapse of time and a voltage generating section (31) connected to the silicon substrate (1) for generating a negative voltage (V1) which decreases in proportion to the lapse of time based on the result of detection (time T) carried out by the time counter (30). Consequently, a semiconductor device capable of suppressing occurrence of total dose effects is obtained.
摘要翻译：电压施加部分（32）连接到硅衬底（1）。辐射到半导体器件的辐射导致大量孔相对于硅层（3）在界面附近的BOX层（2）内积累。孔的积聚量随时间的推移而增加。电压施加部分（32）将随着时间的流逝减小的负电压施加到硅衬底（1）上，以抵消由累积的孔产生的正电场。电压施加部分（32）包括用于检测经过时间的时间计数器（30）和连接到硅衬底（1）的电压产生部分（31），用于产生与基于由时间计数器（30）执行的检测结果（时间T）的时间逝去。因此，获得能够抑制总剂量效应的发生的半导体装置。

18. 发明授权

US06452249B1 Inductor with patterned ground shield 有权
标题翻译：带有图案接地屏蔽的电感器
公开(公告)号：US06452249B1
公开(公告)日：2002-09-17
申请号：US09688812
申请日：2000-10-17
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Yuuichi Hirano , Takashi Ipposhi , Takuji Matsumoto
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Yuuichi Hirano , Takashi Ipposhi , Takuji Matsumoto
IPC分类号： H01L2900
CPC分类号： H01L23/5227 , H01L21/28518 , H01L21/84 , H01L23/645 , H01L27/0688 , H01L27/08 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.
摘要翻译：提供具有电感器的半导体器件。在RF电路部分（RP）中，与设置有螺旋电感器（SI）的区域对应的SOI层（3）中的区域被多个沟槽隔离氧化物（21）分成多个SOI区域电影（11）。沟槽隔离氧化膜（11）通过用氧化硅膜填充从SOI层（3）的表面延伸到掩埋氧化膜（2）的表面的沟槽而形成，并将SOI区域（21 ）彼此。沟槽隔离氧化物膜（11）具有预定的宽度并且被成形为基本上垂直于掩埋氧化膜（2）的表面延伸。半导体器件能够降低静电感应功率耗散和电磁感应功率消耗，并且防止其结构和制造步骤变得复杂。

19. 发明授权

US6035169A Developing device 有权
标题翻译：开发设备
公开(公告)号：US6035169A
公开(公告)日：2000-03-07
申请号：US229175
申请日：1999-01-13
申请人： Koji Miyake , Hideaki Tanaka , Takuji Matsumoto
发明人： Koji Miyake , Hideaki Tanaka , Takuji Matsumoto
IPC分类号： G03G15/08 , G03G15/00
CPC分类号： G03G15/0808 , G03G2215/0607
摘要： In a developing device comprising a developing member for transferring toner onto an electrostatic latent image for visualization, and a developer supplying member for magnetically attracting two-component developer on the peripheral surface for conveyance, and supplying two-component developer or toner to the developing member, the developer will be sufficiently agitated on the developer supplying member, and toner density and amount of toner charge in the two-component developer will be controlled with simple structure. A part of two-component developer, to which toner has been supplied on the developer supplying member, is caused to flow back on the upstream side in the conveying direction within a range in which the attracting force of magnetic poles of the internal member which the developer supplying member has acts. The internal member is caused to be rotationally moved, and a fluctuating magnetic field is formed between the internal member and the magnet arranged to face to it to thereby cause the reflux. Also, a rotating member which mechanically causes the reflux may be provided. Further, it may be possible to rotationally move the magnetic poles of the developer supplying member and to form an alternating electric field between the developer supplying member and an electrode opposite thereto for thereby causing the reflux.
摘要翻译：在包括用于将调色剂转印到用于可视化的静电潜像上的显影部件的显影装置中，以及用于在外周表面上磁吸引双组分显影剂进行输送的显影剂供给部件，并将二组分显影剂或调色剂供应到显影部件，显影剂将在显影剂供应构件上充分搅动，并且以简单的结构控制双组分显影剂中的调色剂浓度和调色剂电荷量。在显影剂供给部件上已经供给调色剂的一部分双组分显影剂在输送方向的上游侧流回到内部部件的磁极的吸引力的范围内开发商供应商有行为。内部构件被旋转移动，并且在内部构件和布置成面对它的磁体之间形成波动的磁场，从而引起回流。而且，可以提供机械地引起回流的旋转构件。此外，可以旋转地移动显影剂供应构件的磁极并且在显影剂供应构件和与其相对的电极之间形成交变电场，从而引起回流。

20. 发明授权

US08526861B2 Image forming apparatus 有权
标题翻译：图像形成装置
公开(公告)号：US08526861B2
公开(公告)日：2013-09-03
申请号：US13279622
申请日：2011-10-24
申请人： Takuji Matsumoto
发明人： Takuji Matsumoto
IPC分类号： G03G21/16 , G03G15/04 , G03G15/08
CPC分类号： G03G15/0879 , G03G15/0813 , G03G15/0886
摘要： An image forming apparatus includes image forming units which are detachably mounted on an apparatus body, and each of which includes an image holding body and a developing unit provided with a developing member that supplies a developer to the electrostatic latent image formed on the surface of the image holding body, shaft members which rotatably support the developing units, urging members which urge the developing members toward the image holding bodies, supply devices which supply developers to the developing units, transport passages which are provided so as to extend toward the developing members and the image holding bodies, and elastic members which form a part of the transport passage and are extensibly deformed so as to absorb the deviation of the relative position between the supply port and the receiving port.
摘要翻译：图像形成装置包括可拆卸地安装在装置主体上的图像形成单元，每个图像形成单元包括图像保持体和显影单元，显影单元设置有显影剂，该显影剂将显影剂供应到形成在该表面上的静电潜像图像保持体，可旋转地支撑显影单元的轴构件，将显影构件朝向图像保持体推动的推动构件，向显影单元供给显影剂的供给装置，设置成朝向显影构件延伸的输送路径，图像保持体和形成传送通道的一部分并且可伸缩变形的弹性构件，以便吸收供给口与接收口之间的相对位置的偏差。

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