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11. 发明授权

US08036326B2 Apparatus and method for cancelling interferences between orthogonal coded signals in mobile communication system 有权
标题翻译：用于消除移动通信系统中的正交编码信号之间的干扰的装置和方法
公开(公告)号：US08036326B2
公开(公告)日：2011-10-11
申请号：US12155395
申请日：2008-06-03
申请人： Donghun Yu , Jun Jin Kong , Sung Chung Park
发明人： Donghun Yu , Jun Jin Kong , Sung Chung Park
IPC分类号： H04L25/08 , H04L1/02
CPC分类号： H04L25/0204 , H04B1/71052 , H04L25/0224 , H04L25/0246
摘要： Apparatuses and methods for cancelling interferences between signals are provided. The apparatuses includes: a receiving unit that receives an orthogonal coded signal from a transmitter and generates a received vector; a channel estimation unit that estimates a state of a wireless channel from the transmitter to the apparatus where the cancelling of the interference between signals is performed and generates a channel state matrix; a Q-R decomposition unit that performs Q-R decomposition with respect to the generated channel state matrix and generates a Q matrix and an R matrix, and generates a decision statistic vector based on the generated Q matrix and the received vector; and a signal determination unit that determines a received signal with interference from the orthogonal coded signal being decreased based on the generated decision statistics vector.
摘要翻译：提供了消除信号间干扰的装置和方法。所述装置包括：接收单元，其从发射机接收正交编码信号并产生接收矢量; 信道估计单元，其估计从发射机到其中执行消除信号之间的干扰的装置的无线信道的状态，并产生信道状态矩阵; Q-R分解单元，对所生成的信道状态矩阵进行Q-R分解，生成Q矩阵和R矩阵，并根据生成的Q矩阵和接收矢量生成判定统计量矢量; 以及信号确定单元，其基于所生成的判定统计矢量，确定来自正交编码信号的干扰的接收信号被减少。

12. 发明授权

US08020081B2 Multi-level cell memory devices using trellis coded modulation and methods of storing data in and reading data from the memory devices 有权
标题翻译：使用网格编码调制的多级单元存储器件以及将数据存储在存储器件中并从其读取数据的方法
公开(公告)号：US08020081B2
公开(公告)日：2011-09-13
申请号：US11802334
申请日：2007-05-22
申请人： Jun Jin Kong , Sung Chung Park , Yun Tae Lee , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun , Dong Ku Kang
发明人： Jun Jin Kong , Sung Chung Park , Yun Tae Lee , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun , Dong Ku Kang
IPC分类号： H03M13/03
CPC分类号： G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/10
摘要： A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.
摘要翻译：多级单元（MLC）存储器件可以包括：MLC存储器单元; 外部编码器，其使用第一编码方案对数据进行编码以生成外部编码比特流; 以及网格编码调制（TCM）调制器，其向MLC存储器单元施加编程脉冲以将数据写入MLC存储器单元。可以通过对外部编码比特流进行TCM调制来生成编程脉冲。一种在MLC存储器件中存储数据，从MLC存储器件读取数据或将数据存储在MLC存储器件中并从MLC存储器件读取数据的方法可以包括：使用第一编码方案对数据进行编码以产生外编码位流; 以及向MLC存储器件的MLC存储器单元施加编程脉冲以将数据写入MLC存储单元。可以通过对外部编码比特流进行TCM调制来生成编程脉冲。

13. 发明申请

US20110213930A1 Multi-level cell memory device and method thereof 有权
标题翻译：多级单元存储装置及其方法
公开(公告)号：US20110213930A1
公开(公告)日：2011-09-01
申请号：US13067099
申请日：2011-05-09
申请人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
IPC分类号： G06F12/08
CPC分类号： G11C11/5621 , G11C7/1006 , G11C29/00
摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
摘要翻译：提供了一种多级单元（MLC）存储器件及其方法。示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。

14. 发明授权

US07957475B2 Dual carrier modulation (DCM) demapper and DCM demapping method 有权
标题翻译：双载波调制（DCM）解映射器和DCM解映射方法
公开(公告)号：US07957475B2
公开(公告)日：2011-06-07
申请号：US11704907
申请日：2007-02-12
申请人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
发明人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
IPC分类号： H04K1/10
CPC分类号： H04L27/2649 , H04L25/022 , H04L25/067 , H04L27/3416
摘要： A DCM demapper and a DCM demapping method are provided. The DCM demapper includes: a basic signal generation unit generating a plurality of basic signals using a signal and channel information of two subcarriers; a soft decision generation unit generating a plurality of soft decisions using the plurality of basic signals; and a soft decision selection unit selecting a soft decision corresponding to each bit of the two subcarriers among the generated soft decisions.
摘要翻译：提供DCM解映射器和DCM解映射方法。 DCM解映射器包括：使用信号和两个子载波的信道信息生成多个基本信号的基本信号生成单元; 软判决生成单元，使用所述多个基本信号生成多个软判决; 以及软判决选择单元，在所生成的软决策中选择与所述两个子载波的每个比特相对应的软判决。

15. 发明申请

US20090177931A1 Memory device and error control codes decoding method 有权
标题翻译：存储器件和错误控制代码解码方法
公开(公告)号：US20090177931A1
公开(公告)日：2009-07-09
申请号：US12153121
申请日：2008-05-14
申请人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
发明人： Seung-Hwan Song , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho , Sung Chung Park
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/141 , G06F11/1012 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C29/00
摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.
摘要翻译：可以提供存储器件和/或错误控制代码（ECC）解码方法。存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。可以通过这样的存储器件来减少ECC解码时间。

16. 发明申请

US20090150751A1 MEMORY SYSTEM THAT USES AN INTERLEAVING SCHEME AND A METHOD THEREOF 有权
标题翻译：使用交互方案的记忆系统及其方法
公开(公告)号：US20090150751A1
公开(公告)日：2009-06-11
申请号：US12256784
申请日：2008-10-23
申请人： Nam Phil Jo , Dong Hyuk Chae , Sung Chung Park , Dong Gu Kang
发明人： Nam Phil Jo , Dong Hyuk Chae , Sung Chung Park , Dong Gu Kang
IPC分类号： G06F12/00 , H03M13/05 , G06F11/10
CPC分类号： G11C7/1042 , G06F11/1068 , G06F13/4239
摘要： A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.
摘要翻译：存储器系统包括多个存储器件，被配置为控制多个存储器件的控制器以及连接在多个存储器件与控制器之间的至少一个通道。所述至少一个通道包括与所述多个存储器件连接的输入/输出数据线和控制信号线以及分别连接到所述多个存储器件中的每一个的芯片使能信号线，其中所述芯片使能信号线使得能够多个存储设备独立。控制器向多个存储器件之一发送读取命令或程序命令，并且当多个存储器件中的一个存储器件响应于读取命令执行内部读取操作时，控制器从另一个多个存储器件，或者当多个存储器件中的一个存储器件响应于程序命令执行内部程序操作时，控制器将数据编程到多个存储器件中的另一个。

17. 发明申请

US20090122929A1 Apparatus and method for cancelling interferences between orthogonal coded signals in mobile communication system 有权
标题翻译：用于消除移动通信系统中的正交编码信号之间的干扰的装置和方法
公开(公告)号：US20090122929A1
公开(公告)日：2009-05-14
申请号：US12155395
申请日：2008-06-03
申请人： Donghun Yu , Jun Jin Kong , Sung Chung Park
发明人： Donghun Yu , Jun Jin Kong , Sung Chung Park
IPC分类号： H04B1/10
CPC分类号： H04L25/0204 , H04B1/71052 , H04L25/0224 , H04L25/0246
摘要： Apparatuses and methods for cancelling interferences between signals are provided. The apparatuses includes: a receiving unit that receives an orthogonal coded signal from a transmitter and generates a received vector; a channel estimation unit that estimates a state of a wireless channel from the transmitter to the apparatus where the cancelling of the interference between signals is performed and generates a channel state matrix; a Q-R decomposition unit that performs Q-R decomposition with respect to the generated channel state matrix and generates a Q matrix and an R matrix, and generates a decision statistic vector based on the generated Q matrix and the received vector; and a signal determination unit that determines a received signal with interference from the orthogonal coded signal being decreased based on the generated decision statistics vector.
摘要翻译：提供了消除信号间干扰的装置和方法。所述装置包括：接收单元，其从发射机接收正交编码信号并产生接收矢量; 信道估计单元，其估计从发射机到其中执行消除信号之间的干扰的装置的无线信道的状态，并产生信道状态矩阵; Q-R分解单元，对所生成的信道状态矩阵进行Q-R分解，生成Q矩阵和R矩阵，并根据生成的Q矩阵和接收矢量生成判定统计量矢量; 以及信号确定单元，其基于所生成的判定统计矢量，确定来自正交编码信号的干扰的接收信号被减少。

18. 发明申请

US20090046510A1 Apparatus and method for multi-bit programming 审中-公开
标题翻译：多位编程的装置和方法
公开(公告)号：US20090046510A1
公开(公告)日：2009-02-19
申请号：US12007775
申请日：2008-01-15
申请人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Heeseok Eun , Dong Hyuk Chae , Kyoung Lae Cho
发明人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Heeseok Eun , Dong Hyuk Chae , Kyoung Lae Cho
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5641
摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus may include: a first programming unit that stores data corresponding to a number of first bits in at least one first memory cell that may be connected to at least one first bit line; and a second programming unit that stores data corresponding to a number of second bits in at least one second memory cell that may be connected to at least one second bit line. Through this, it may be possible to improve data reliability and increase a number of bits to be stored in the entire memory cell.
摘要翻译：提供了多位编程设备和方法。一种多位编程设备可以包括：第一编程单元，其存储对应于可连接到至少一个第一位线的至少一个第一存储器单元中的多个第一位的数据; 以及第二编程单元，其将可能连接到至少一个第二位线的至少一个第二存储器单元中的与第二位数相对应的数据存储。由此，可以提高数据可靠性并增加要存储在整个存储单元中的位数。

19. 发明申请

US20080285343A1 Memory cell programming method and semiconductor device for simultaneously programming a plurality of memory block groups 有权
标题翻译：用于同时编程多个存储块组的存储单元编程方法和半导体器件
公开(公告)号：US20080285343A1
公开(公告)日：2008-11-20
申请号：US12081568
申请日：2008-04-17
申请人： Ju-hee Park , Jae-woong Hyun , Yoon-dong Park , Kyoung-lae Cho , Sung-jae Byun , Seung-hwan Song , Jun-jin Kong , Sung-chung Park
发明人： Ju-hee Park , Jae-woong Hyun , Yoon-dong Park , Kyoung-lae Cho , Sung-jae Byun , Seung-hwan Song , Jun-jin Kong , Sung-chung Park
IPC分类号： G11C16/04 , G11C8/00
CPC分类号： H01L29/7883 , G11C16/10
摘要： Provided are a memory cell programming method and a semiconductor device which may be capable of simultaneously writing a bit of data and then another bit of the data to a plurality of memory blocks. The memory programming method, in which M bits of data are written to a plurality of memory blocks, may include a data division operation and a data writing operation where M may be a natural number. In the data division operation, the plurality of memory blocks may be divided into a plurality of memory block groups. In the data writing operation, an ith bit of the data may be simultaneously written to two or more memory block groups from among the plurality memory block groups, and then an i+1th bit of the data may be simultaneously written to the two or more memory block groups from among the plurality memory block groups, where i is a natural number less than M.
摘要翻译：提供了一种存储器单元编程方法和半导体器件，其可以能够同时将数据位和数据的另一位写入多个存储块。其中将M位数据写入多个存储块的存储器编程方法可以包括数据分割操作和数据写入操作，其中M可以是自然数。在数据划分操作中，多个存储块可以被划分为多个存储块组。在数据写入操作中，数据的第i / O位可以被同时写入到多个存储块组之中的两个或更多个存储块组，然后i + 1＆lt; / SUP>位可以从多个存储块组中的两个或更多个存储块组同时写入，其中i是小于M的自然数。

20. 发明申请

US20080285340A1 Apparatus for reading data and method using the same 有权
标题翻译：用于读取数据的装置和使用该装置的方法
公开(公告)号：US20080285340A1
公开(公告)日：2008-11-20
申请号：US12007921
申请日：2008-01-17
申请人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
发明人： Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
IPC分类号： G11C16/06 , G11C7/02
CPC分类号： G11C16/26 , G11C7/1006 , G11C11/5642
摘要： Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.
摘要翻译：公开了一种用于读取数据的装置和方法。根据示例实施例的用于读取数据的方法包括将存储器单元的阈值电压与第一边界电压进行比较，将阈值电压与具有比第一边界电压的电压电平更高的电压电平的第二边界电压进行比较，以及确定数据所述存储单元基于所述阈值电压，所述第一边界电压和所述第二边界电压。

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