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11. 发明授权

US07986251B2 Input/output (IO) interface and method of transmitting IO data 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US07986251B2
公开(公告)日：2011-07-26
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M5/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多条并行数据中的每一条进行编码并产生多条编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

12. 发明申请

US20110158030A1 METHOD AND APPARATUS FOR TUNING PHASE OF CLOCK SIGNAL 有权
标题翻译：用于调谐时钟信号的方法和装置
公开(公告)号：US20110158030A1
公开(公告)日：2011-06-30
申请号：US13042244
申请日：2011-03-07
申请人： Seung Jun BAE , Kwang Il Park , Sam Young Bang , Gil Shin Moon , Ki Woong Yeom
发明人： Seung Jun BAE , Kwang Il Park , Sam Young Bang , Gil Shin Moon , Ki Woong Yeom
IPC分类号： G11C8/00
CPC分类号： H03L7/06 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.
摘要翻译：一种用于调谐具有与主时钟信号不同的频率的数据时钟信号的相位的方法和装置。调谐方法包括：通过接收数据时钟信号进行粗调，分割数据时钟信号以产生与主时钟信号具有相同频率的分频时钟信号，重新移位分频时钟信号以产生多相频率 - 以预定的相位间隔分配时钟信号，将多相分频时钟信号中的每一个的相位与主时钟信号的相位进行比较，并且基于比较结果确定相移量，并且通过比较相位对应于与主时钟信号的相位的相移量相对应的多相分频时钟信号，并且基于比较结果调整数据时钟信号的相位预定相位步长。

13. 发明授权

US07961121B2 Transmitting/receiving methods and systems with simultaneous switching noise reducing preambles 有权
标题翻译：具有同步开关噪声降低前导码的发射/接收方法和系统
公开(公告)号：US07961121B2
公开(公告)日：2011-06-14
申请号：US12824156
申请日：2010-06-26
申请人： Seung-Jun Bae , Seong-Jin Jang
发明人： Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03M5/00
CPC分类号： H03M5/145
摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.
摘要翻译：通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

14. 发明申请

US20110128170A1 Semiconductor devices, a system including semiconductor devices and methods thereof 审中-公开
标题翻译：半导体器件，包括半导体器件的系统及其方法
公开(公告)号：US20110128170A1
公开(公告)日：2011-06-02
申请号：US12923858
申请日：2010-10-12
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
IPC分类号： H03M7/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
摘要翻译：提供半导体器件，包括所述半导体器件的系统及其方法。半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，根据给定的伪随机序列排列的加扰顺序。所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。然后可以发送平衡和加扰的接收数据。示例半导体器件可以以任何顺序执行加扰和平衡操作。类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

15. 发明授权

US07902887B2 Method and apparatus for tuning phase of clock signal 有权
标题翻译：调谐时钟信号相位的方法和装置
公开(公告)号：US07902887B2
公开(公告)日：2011-03-08
申请号：US12385431
申请日：2009-04-08
申请人： Seung Jun Bae , Kwang Il Park , Sam Young Bang , Gil Shin Moon , Ki Woong Yeom
发明人： Seung Jun Bae , Kwang Il Park , Sam Young Bang , Gil Shin Moon , Ki Woong Yeom
IPC分类号： H03L7/06
CPC分类号： H03L7/06 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.
摘要翻译：一种用于调谐具有与主时钟信号不同的频率的数据时钟信号的相位的方法和装置。调谐方法包括：通过接收数据时钟信号进行粗调，分割数据时钟信号以产生与主时钟信号具有相同频率的分频时钟信号，重新移位分频时钟信号以产生多相频率 - 以预定的相位间隔分配时钟信号，将多相分频时钟信号中的每一个的相位与主时钟信号的相位进行比较，并且基于比较结果确定相移量，并且通过比较相位对应于与主时钟信号的相位的相移量相对应的多相分频时钟信号，并且基于比较结果调整数据时钟信号的相位预定相位步长。

16. 发明申请

US20100329041A1 SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT 有权
标题翻译：具有节能效果的半导体存储器件
公开(公告)号：US20100329041A1
公开(公告)日：2010-12-30
申请号：US12797791
申请日：2010-06-10
申请人： Young-Soo SOHN , Kwang-IL Park , Kyoung-Ho Kim , Seung-Jun Bae
发明人： Young-Soo SOHN , Kwang-IL Park , Kyoung-Ho Kim , Seung-Jun Bae
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1084 , G11C8/18 , G11C2207/2227 , G11C2207/2272
摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。存储单元阵列包括多个存储单元，并被配置为存储数据。当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号设备。数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

17. 发明授权

US07830280B2 Semiconductor devices, a system including semiconductor devices and methods thereof 有权
标题翻译：半导体器件，包括半导体器件的系统及其方法
公开(公告)号：US07830280B2
公开(公告)日：2010-11-09
申请号：US12453109
申请日：2009-04-29
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-Il Park , Woo-Jin Lee
IPC分类号： H03M5/00
CPC分类号： H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.
摘要翻译：提供半导体器件，包括所述半导体器件的系统及其方法。半导体器件的示例可以接收被调度用于传输的数据，对接收到的数据内的比特数进行加扰，根据给定的伪随机序列排列的加扰顺序。所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。然后可以发送平衡和加扰的接收数据。示例半导体器件可以以任何顺序执行加扰和平衡操作。类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

18. 发明授权

US07817714B2 Integrating receiver having adaptive feedback equalizer function to simultaneously remove inter-symbol interference and high frequency noises and system having the same 有权
标题翻译：具有自适应反馈均衡器功能的积分接收机同时消除符号间干扰和高频噪声，并具有相同的系统
公开(公告)号：US07817714B2
公开(公告)日：2010-10-19
申请号：US11623517
申请日：2007-01-16
申请人： Seung Jun Bae , Hong June Park
发明人： Seung Jun Bae , Hong June Park
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H03G11/04 , H04B3/04
CPC分类号： H04L25/03057
摘要： Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used. Accordingly, the present invention can be applied to not only a DRAM interface system but also a serial communication between chips.
摘要翻译：提供一种具有自适应判决反馈均衡器功能的积分接收器和具有该自适应判决反馈均衡器功能的系统。积分接收器可以同时消除高速DRAM数据传输系统中的符号间干扰（ISI）和高频噪声。积分接收器在存在于信道中的ISI被去除的状态中降低数据错误判定的可能性，以增加接收机的信噪比（SNR），从而最大运算速度增加即使在噪音很大的环境中也是如此。还提供了一种获得适合于积分接收器的均衡器系数的方法以及通过使用单端传输方法中的积分器来获得参考电压的方法。另外，为了增加判定反馈均衡器的速度，使用先行方法。在这种方法中，使用包括多路复用器的具有高速度的触发器。因此，本发明不仅可以应用于DRAM接口系统，还可以应用于芯片之间的串行通信。

19. 发明申请

US20100259426A1 TRANSMITTING/RECEIVING METHODS AND SYSTEMS WITH SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES 有权
标题翻译：同时切换噪声的发射/接收方法和系统
公开(公告)号：US20100259426A1
公开(公告)日：2010-10-14
申请号：US12824156
申请日：2010-06-26
申请人： Seung-Jun Bae , Seong-Jin Jang
发明人： Seung-Jun Bae , Seong-Jin Jang
IPC分类号： H03M5/00
CPC分类号： H03M5/145
摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.
摘要翻译：通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

20. 发明授权

US07737748B2 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US07737748B2
公开(公告)日：2010-06-15
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03K3/017
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

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