专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07750295B2 Extractor for an microcolumn, an alignment method for an extractor aperture to an electron emitter, and a measuring method and an alignment method using thereof 有权
标题翻译：用于微柱的提取器，用于提取器孔到电子发射器的对准方法，以及使用其的测量方法和对准方法
公开(公告)号：US07750295B2
公开(公告)日：2010-07-06
申请号：US10538284
申请日：2003-12-30
申请人： Ho Soeb Kim , Seung Joon Ahn , Dae Wook Kim
发明人： Ho Soeb Kim , Seung Joon Ahn , Dae Wook Kim
IPC分类号： H01J37/352
CPC分类号： H01J3/028 , H01J3/10 , H01J37/067 , H01J37/15 , H01J2237/1205 , H01J2237/1501 , H01J2237/1502 , H01J2237/24465 , H01J2237/24507
摘要： The present invention provides a new extractor for a micro-column and an alignment method of the aperture of the extractor and an electron emitter for a micro-column. Further, the present invention provides a measuring system, a method for measuring, and an alignment method using the principle of the alignment.
摘要翻译：本发明提供了用于微柱的新提取器和提取器的孔径和用于微柱的电子发射器的对准方法。此外，本发明提供了使用对准原理的测量系统，测量方法和对准方法。

12. 发明授权

US5963805A Method for forming integrated circuit capacitors including dual layer electrodes 失效
标题翻译：用于形成包括双层电极的集成电路电容器的方法
公开(公告)号：US5963805A
公开(公告)日：1999-10-05
申请号：US884149
申请日：1997-06-27
申请人： Man-sug Kang , Seung-joon Ahn
发明人： Man-sug Kang , Seung-joon Ahn
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/84
摘要： A method for forming an integrated circuit capacitor includes the steps of forming a first electrode layer on a substrate wherein the first electrode has a first dopant concentration, and forming a second electrode layer on the first electrode layer opposite the substrate. The second electrode layer has a second dopant concentration different from the first dopant concentration. In addition, a portion of the second electrode layer is converted to a hemispherical grain layer. More particularly, the first dopant concentration is greater than the second dopant concentration. Related structures are also discussed.
摘要翻译：形成集成电路电容器的方法包括以下步骤：在基板上形成第一电极层，其中第一电极具有第一掺杂剂浓度，并且在与基板相对的第一电极层上形成第二电极层。第二电极层具有不同于第一掺杂剂浓度的第二掺杂剂浓度。此外，第二电极层的一部分被转换为半球形晶粒层。更具体地，第一掺杂剂浓度大于第二掺杂剂浓度。还讨论了相关结构。

13. 发明授权

US08482331B2 Open loop type delay locked loop and method for operating the same 失效
标题翻译：开环型延时锁定环及其操作方法
公开(公告)号：US08482331B2
公开(公告)日：2013-07-09
申请号：US12832549
申请日：2010-07-08
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03H11/26
CPC分类号： H03K5/135 , H03K2005/00104
摘要： An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.
摘要翻译：开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟响应代码值。

14. 发明授权

US08451037B2 Duty cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US08451037B2
公开(公告)日：2013-05-28
申请号：US13048185
申请日：2011-03-15
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为通过响应于控制信号校正输入时钟信号的占空比来产生校正时钟信号;占空比检测单元，被配置为检测校正时钟的占空比信号并输出检测信号，以及控制信号生成单元，被配置为响应于检测信号而产生控制信号。

15. 发明申请

US20120154002A1 DELAY LOCKED LOOP 失效
标题翻译：延迟锁定环
公开(公告)号：US20120154002A1
公开(公告)日：2012-06-21
申请号：US13400967
申请日：2012-02-21
申请人： Seung-Joon AHN , Jong-Chern Lee
发明人： Seung-Joon AHN , Jong-Chern Lee
IPC分类号： H03L7/08
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

16. 发明授权

US08143925B2 Delay locked loop 失效
标题翻译：延迟锁定环路
公开(公告)号：US08143925B2
公开(公告)日：2012-03-27
申请号：US12753442
申请日：2010-04-02
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

17. 发明申请

US20110156767A1 DELAY LOCKED LOOP AND METHOD FOR DRIVING THE SAME 有权
标题翻译：延迟锁定环及其驱动方法
公开(公告)号：US20110156767A1
公开(公告)日：2011-06-30
申请号：US12755949
申请日：2010-04-07
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03L7/0814 , H03L7/07
摘要： A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.
摘要翻译：延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。编码单元被配置为对延迟脉冲进行编码并输出代码值。延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

18. 发明申请

US20110156766A1 DELAY LOCKED LOOP 失效
标题翻译：延迟锁定环
公开(公告)号：US20110156766A1
公开(公告)日：2011-06-30
申请号：US12753442
申请日：2010-04-02
申请人： Seung-Joon AHN , Jong-Chern Lee
发明人： Seung-Joon AHN , Jong-Chern Lee
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
摘要翻译：延迟锁定环包括复制延迟振荡器单元，除法单元，脉冲发生单元，代码值输出单元和延迟线。复制延迟振荡器单元产生具有对应于复制延迟的周期的复制振荡信号。分割单元接收复制振荡信号和时钟信号，并响应于延迟锁定检测信号，以第一或第二比例对复制振荡信号和时钟信号进行分频。脉冲产生单元生成具有对应于用于引起延迟锁定的延迟量的脉冲宽度的延迟脉冲。代码值输出单元响应于延迟锁定检测信号调整与延迟脉冲的脉冲宽度对应的代码值。延迟线响应于代码值延迟时钟信号。

19. 发明申请

US20100244920A1 DELAY CIRCUIT 失效
标题翻译：延时电路
公开(公告)号：US20100244920A1
公开(公告)日：2010-09-30
申请号：US12491567
申请日：2009-06-25
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.
摘要翻译：延迟电路包括第一和第二选择性延迟级，每个延迟阶段包括多个单位延迟单元以延迟施加到其上的信号; 以及延迟控制单元，被配置为响应于第一和第二选择信号的代码组合，选择性地将输入信号施加到第一选择延迟级或第二选择性延迟级，并产生输出信号。

20. 发明申请

US20090200482A1 Method for Focusing Electron Beam in Electron Column 有权
标题翻译：电子束聚焦电子束的方法
公开(公告)号：US20090200482A1
公开(公告)日：2009-08-13
申请号：US12096095
申请日：2006-12-05
申请人： Ho Seob Kim , Seung Joon Ahn , Dae Wook Kim , Young Chul Kim
发明人： Ho Seob Kim , Seung Joon Ahn , Dae Wook Kim , Young Chul Kim
IPC分类号： H01J3/14
CPC分类号： H01J37/12 , B82Y10/00 , B82Y40/00 , H01J37/3174
摘要： The present invention relates to a method for improving focusing in an electron column that generates an electron beam. The method for controlling the focusing of an electron beam in according to the present invention reduces the spot size of the electron beam when the electron beam reaches a specimen, so that resolution can be increased and the line width of a pattern in a semiconductor lithography process can be reduced, with the result that the performance of the electron can be improved.
摘要翻译：本发明涉及一种改善产生电子束的电子束聚焦的方法。根据本发明的用于控制电子束的聚焦的方法当电子束到达样本时减小了电子束的光斑尺寸，从而可以提高分辨率，并且半导体光刻工艺中的图案的线宽可以减少，结果可以提高电子的性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式