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11. 发明申请

US20120278372A1 Cryptographic Random Number Generator Using Finite Field Operations 审中-公开
标题翻译：使用有限域操作的加密随机数生成器
公开(公告)号：US20120278372A1
公开(公告)日：2012-11-01
申请号：US13494636
申请日：2012-06-12
申请人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
发明人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
IPC分类号： G06F7/58 , G06F1/02
CPC分类号： G06F7/588 , G06F7/724 , H04L9/0861
摘要： An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.
摘要翻译：在提供快速，紧凑和密码强的随机数发生器的集成电路芯片的各种说明性实施例中提供了一种装置和方法。在一个说明性实施例中，装置包括初始随机源和与初始随机源通信连接的后处理块。后处理块被配置为从初始随机源接收信号，以将一个或多个有限场操作施加到信号以产生输出，并且在该说明性视图中通过输出通道提供基于输出的输出信号实施例。

12. 发明申请

US20110067982A1 MEMS-BASED SWITCHING 有权
标题翻译：基于MEMS的切换
公开(公告)号：US20110067982A1
公开(公告)日：2011-03-24
申请号：US12562812
申请日：2009-09-18
申请人： Herman Schmit , Sergey Gribok
发明人： Herman Schmit , Sergey Gribok
IPC分类号： H01H57/00
CPC分类号： H01H59/0009
摘要： A MEMS-based switching device may be used to implement an interconnect switch in a programmable integrated circuit device. Such a MEMS-based device may include a deformable cantilever that may form a closed or open circuit to thereby implement switching functionality.
摘要翻译：可以使用基于MEMS的开关装置来实现可编程集成电路装置中的互连开关。这种基于MEMS的装置可以包括可形成闭合或开路的可变形悬臂，从而实现切换功能。

13. 发明授权

US07913149B2 Low complexity LDPC encoding algorithm 有权
标题翻译：低复杂度LDPC编码算法
公开(公告)号：US07913149B2
公开(公告)日：2011-03-22
申请号：US11613256
申请日：2006-12-20
申请人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
发明人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
摘要翻译：通过计算x：= Au来计算二进制源消息u，计算y：= B'x，解析p的等式Dp = y，并且并入u和p以产生编码的二进制消息v，其中A是一个仅由置换子矩阵构成的矩阵，B'是仅由循环置换子矩阵形成的矩阵，D是形式为D =（T 0 ... 0 0 0 T ... 0 0 ...... ...... 0 0 ... T 0 II ... II）其中T是双对角，循环子矩阵，I是身份子矩阵。

14. 发明申请

US20090303093A1 SYSTEMS AND METHODS FOR PIPELINED ANALOG TO DIGITAL CONVERSION 有权
标题翻译：用于管道模拟到数字转换的系统和方法
公开(公告)号：US20090303093A1
公开(公告)日：2009-12-10
申请号：US12134523
申请日：2008-06-06
申请人： Sergey Gribok , Choshu Ito , William Loh , Erik Chmelar
发明人： Sergey Gribok , Choshu Ito , William Loh , Erik Chmelar
IPC分类号： H03M1/00
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种流水线模数转换器，其包括两个或更多个比较器。比较器中的第一个可操作以在断言第一时钟时将模拟输入与第一参考电压进行比较，并且第二比较器可用于在断言第二时钟时将模拟输入与第二参考电压进行比较。流水线模数转换器还包括具有至少第一层多路复用器和第二层多路复用器的复用器树。第一层多路复用器接收第一比较器的输出和第二比较器的输出，并且第二层多路复用器接收从第一层多路复用器导出的输出。第二层复用器提供输出位。位使能集合用作对第一层多路复用器和第二层多路复用器的选择器输入，并且位使能集包括来自先前位周期的一个或多个输出位。

15. 发明申请

US20080168334A1 Low Complexity LDPC Encoding Algorithm 有权
公开(公告)号：US20080168334A1
公开(公告)日：2008-07-10
申请号：US11613256
申请日：2006-12-20
申请人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
发明人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B″x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 ⋯ 0 0 0 T ⋯ 0 0 ⋯ ⋯ ⋯ ⋯ ⋯ 0 0 ⋯ T 0 I I ⋯ I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.

16. 发明授权

US07308633B2 Master controller architecture 失效
标题翻译：主控制器架构
公开(公告)号：US07308633B2
公开(公告)日：2007-12-11
申请号：US10999720
申请日：2004-11-30
申请人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
发明人： Alexandre Andreev , Sergey Gribok , Anatoli Bolotov
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/72
摘要： A master controller for an RRAM subsystem. An interface communicates with at least one RRAM controller. A main control unit selects and implements test and repair operations on the RRAM subsystem through the RRAM controller. A timer determines a maximum number of test and repair operations that can be implemented within a given time. Thus, a master controller is included in the RRAM subsystem. The master controller has a relatively simple interface, and performs test and repair operations on the RRAM subsystem. The advantages of using the master controller include an elimination of additional test ports, simplification of the process of preparing the test vectors for RRAM testing, and the master controller is able to accumulate test results and initiate repairs based on those results. In this manner, the RRAM subsystem has a self-repair functionality.
摘要翻译：用于RRAM子系统的主控制器。接口与至少一个RRAM控制器通信。主控单元通过RRAM控制器对RRAM子系统进行测试和修复操作。定时器确定在给定时间内可以实现的最大测试和修复操作数。因此，主控制器包含在RRAM子系统中。主控制器具有相对简单的接口，并对RRAM子系统执行测试和修复操作。使用主控制器的优点包括消除额外的测试端口，简化了用于RRAM测试的测试向量的准备过程，并且主控制器能够根据这些结果积累测试结果并启动修复。以这种方式，RRAM子系统具有自修复功能。

17. 发明申请

US20110173510A1 Parallel LDPC Decoder 审中-公开
标题翻译：并行LDPC解码器
公开(公告)号：US20110173510A1
公开(公告)日：2011-07-14
申请号：US13069105
申请日：2011-03-22
申请人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
发明人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
IPC分类号： H03M13/11 , G06F11/10
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/114
摘要： An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
摘要翻译：实现迭代消息传递算法的LDPC解码器，其中改进包括流水线架构，使得解码器在列操作期间累积行操作的结果，使得不需要额外的时间和存储器来存储超过该操作的行操作的结果列操作需要。

18. 发明申请

US20100030835A1 Variable Node Processing Unit 失效
标题翻译：可变节点处理单元
公开(公告)号：US20100030835A1
公开(公告)日：2010-02-04
申请号：US12185404
申请日：2008-08-04
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
IPC分类号： G06F11/00
CPC分类号： G06F7/575 , H03M13/1102 , H03M13/1111 , H03M13/1117
摘要： A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.
摘要翻译：具有N + 1个输入的可变节点处理单元，其具有至少第一组双输入加法器和独立的最后一组双输入加法器，其中加法器组串联配置。

19. 发明申请

US20090287980A1 Computational Architecture for Soft Decoding 审中-公开
标题翻译：软解码的计算架构
公开(公告)号：US20090287980A1
公开(公告)日：2009-11-19
申请号：US12121824
申请日：2008-05-16
申请人： Sergey Gribok , Alexander Andreev
发明人： Sergey Gribok , Alexander Andreev
IPC分类号： G06F11/08 , G06F15/76 , G06F9/02
CPC分类号： H04L1/0052 , G06F11/1008 , G06F15/7867
摘要： A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation.
摘要翻译：用于软解码的设备包含一组操作元件，每个操作元件能够执行若干不同功能之一。操作元件可以被动态配置为具有到寄存器，存储器位置和其他操作元件的输入和输出连接，以在软解码方案中执行各种步骤。在许多情况下，操作元件可以被配置为在可以并行执行许多操作序列的流水线模式下操作。可以在每个时钟周期重新配置一些实施例，以在解码操作期间执行不同的步骤。该设备可以用于执行具有可编程处理器的灵活性但是硬件实现的吞吐量的几种不同的软解码方案。

20. 发明申请

US20080134008A1 Parallel LDPC Decoder 有权
标题翻译：并行LDPC解码器
公开(公告)号：US20080134008A1
公开(公告)日：2008-06-05
申请号：US11565670
申请日：2006-12-01
申请人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
发明人： Alexander Andreev , Igor Vikhliantsev , Sergey Gribok
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/114
摘要： An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
摘要翻译：实现迭代消息传递算法的LDPC解码器，其中改进包括流水线架构，使得解码器在列操作期间累积行操作的结果，使得不需要额外的时间和存储器来存储超过该操作的行操作的结果列操作需要。

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