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11. 发明申请

WO2002086973A2 NANOELECTRONIC DEVICES AND CIRCUITS 审中-公开
标题翻译：纳米电子设备和电路
公开(公告)号：WO2002086973A2
公开(公告)日：2002-10-31
申请号：PCT/GB2002/001807
申请日：2002-04-18
申请人： BTG INTERNATIONAL LIMITED , SONG, Aimin , OMLING, Pär
发明人： SONG, Aimin , OMLING, Pär
IPC分类号： H01L27/00
CPC分类号： B82Y10/00 , H01L29/66075 , H01L29/66204 , H01L29/6631 , H01L29/66469 , H01L29/7393 , H01L29/772 , H01L29/775 , H01L29/861
摘要： Diode devices with superior and pre-settable characteristics and of nanometric dimensions, comprise etched insulative lines (8, 16, 18) in a conductive substrate to define between the lines charge carrier flow paths, formed as elongate channels (20) at least 100 nm long and less than 100 nm wide. The current-voltage characteristic of the diode devices are similar to a conventional diode, but both the threshold voltage (from 0V to a few volts) and the current level (from nA to μA) can be tuned by orders of magnitude by changing the device geometry. Standard silicon wafers can be used as substrates. A full family of logic gates, such as OR, AND, and NOT, can be constructed based on this device solely by simply etching insulative lines in the substrate.
摘要翻译：具有优异和可预设的特性和纳米尺寸的二极管器件包括导电衬底中的蚀刻绝缘线（8,16,18），以在线之间限定电荷载流子流动路径，其形成为至少100nm的细长通道（20）长且小于100nm宽。二极管器件的电流 - 电压特性类似于常规二极管，但是阈值电压（从0V到几伏特）和电流电平（从nA到μA）都可以通过改变数量级来调节数量级设备几何。标准硅晶片可用作基板。逻辑门的全系列，例如OR，AND和NOT，可以仅通过简单地蚀刻衬底中的绝缘线来基于该器件构造。

12. 发明申请

WO2010086651A1 ELECTRONIC DEVICES, CIRCUITS AND THEIR MANUFACTURE 审中-公开
标题翻译：电子设备，电路及其制造
公开(公告)号：WO2010086651A1
公开(公告)日：2010-08-05
申请号：PCT/GB2010/050123
申请日：2010-01-27
申请人： NANO EPRINT LIMITED , SONG, Aimin , WHITELEGG, Stephen , SUN, Yanming , LIN, Shiwei
发明人： SONG, Aimin , WHITELEGG, Stephen , SUN, Yanming , LIN, Shiwei
IPC分类号： H01L51/00 , H01L27/28 , H01L51/05
CPC分类号： H01L51/0014 , H01L21/764 , H01L27/28 , H01L51/0023 , H01L51/0036 , H01L51/0575 , H01L2251/105
摘要： A method of manufacturing an electronic device, comprising a layer of semiconductive material and at least one insulative feature arranged to interrupt the layer of semiconductive material, comprises: providing a layer of semiconductive material, and a layer of compressible material supporting the layer of semiconductive material; and forming the or each insulative feature by a method comprising displacing a respective selected portion of the layer of semiconductive material towards the compressible material so as to compress compressible material under the or each displaced portion and separate at least partly the or each displaced portion from undisplaced semiconductive material.
摘要翻译：一种制造电子器件的方法，包括半导体材料层和布置成中断半导体材料层的至少一个绝缘特征，包括：提供半导体材料层，以及支撑半导体材料层的可压缩材料层 ; 以及通过包括使所述半导体材料层的相应选定部分朝向所述可压缩材料移位以便压缩所述或每个移位部分下方的可压缩材料并且至少部分地将所述或每个位移部分与未置换的部分分离的方法来形成所述绝缘或每个绝缘特征半导体材料。

13. 发明申请

WO2010049728A1 FETs, SEMICONDUCTOR DEVICES AND THEIR METHODS OF MANUFACTURE 审中-公开
标题翻译： FET，半导体器件及其制造方法
公开(公告)号：WO2010049728A1
公开(公告)日：2010-05-06
申请号：PCT/GB2009/051444
申请日：2009-10-27
申请人： NANO EPRINT LIMITED , SONG, Aimin , SUN, Yanming , LIN, Shiwei
发明人： SONG, Aimin , SUN, Yanming , LIN, Shiwei
IPC分类号： H01L51/05
CPC分类号： H01L51/0529 , C08G2261/3142 , C08G2261/3223 , C08G2261/3422 , C08G2261/92 , H01L51/0036 , H01L51/052 , H01L51/0545
摘要： A field effect transistor comprises: a source; a drain; semiconductor material arranged to provide an electrical conduction path between the source and the drain; and a gate arranged such that an electrical conductivity of the conduction path can be modulated by application of a voltage to the gate. The FET further comprises: a substantially fixed distribution of charge arranged to produce an electric field; and insulative material separating the distribution of charge from the semiconductor material, the arrangement being such that the semiconductor material is exposed to the electric field and the electrical conductivity of the conduction path is determined at least in part by the voltage applied to the gate and by the charge distribution. The distribution of charge may be provided by a monolayer in which each molecule has a fixed polarisation, and a method of manufacturing the FET may include controlling a thickness of an insulating layer separating the charge distribution from the semiconductive material to tune the threshold voltage of the FET.
摘要翻译：一种场效应晶体管，包括：源极; 排水半导体材料布置成在源极和漏极之间提供导电路径; 以及布置成使得可以通过向栅极施加电压来调制导电路径的导电性的栅极。 FET还包括：布置成产生电场的电荷的基本上固定的分布; 以及绝缘材料，其将电荷分布与半导体材料分离，该布置使得半导体材料暴露于电场，并且导电路径的导电性至少部分地由施加于栅极的电压和电荷分布。电荷的分布可以由其中每个分子具有固定极化的单层提供，并且制造FET的方法可以包括控制将电荷分布与半导体材料分离的绝缘层的厚度，以调节电极的阈值电压 FET。

14. 发明申请

WO2010013064A1 ELECTRONIC DEVICE MANUFACTURING METHOD 审中-公开
标题翻译：电子设备制造方法
公开(公告)号：WO2010013064A1
公开(公告)日：2010-02-04
申请号：PCT/GB2009/050960
申请日：2009-07-31
申请人： NANO EPRINT LIMITED , SONG, Aimin , WHITELEGG, Stephen , SUN, Yanming
发明人： SONG, Aimin , WHITELEGG, Stephen , SUN, Yanming
IPC分类号： H01L51/00
CPC分类号： H01L51/0014 , H01L2251/105
摘要： A method of manufacturing an electronic device comprising a device substrate supporting a patterned layer of active material is disclosed. The method comprises: providing a device substrate having a substantially uniform surface; patterning said surface; providing an unpatterned layer of active material on a carrier substrate; and forming a correspondingly patterned layer of active material on the patterned device substrate surface by urging the device substrate and carrier substrate together so as to bring the patterned device substrate surface into contact with the unpatterned layer of active material, and then separating the device substrate and carrier substrate.
摘要翻译：公开了一种制造包括支撑活性材料的图案化层的器件衬底的电子器件的方法。该方法包括：提供具有基本上均匀表面的器件衬底; 图案化所述表面; 在载体基底上提供未图案化的活性材料层; 以及通过将所述器件衬底和载体衬底一起施加在所述图案化器件衬底表面上来形成相应图案化的活性材料层，以使所述图案化器件衬底表面与所述未图案化的活性材料层接触，然后将所述器件衬底和载体衬底。

15. 发明申请

WO2004087933A2 A NOVEL ENCODING METHOD FOR "ONE-BEAD ONE-COMPOUND" COMBINATORIAL LIBRARIES 审中-公开
标题翻译： “一珠一体”组合图书馆的新编码方法
公开(公告)号：WO2004087933A2
公开(公告)日：2004-10-14
申请号：PCT/US2004009530
申请日：2004-03-25
申请人： UNIV CALIFORNIA , LAM KIT S , SONG AIMIN , LEBRILLA CARLITO B , ZHANG JINHUA
发明人： LAM KIT S , SONG AIMIN , LEBRILLA CARLITO B , ZHANG JINHUA
IPC分类号： B01J19/00 , C12P20060101 , C12Q1/68 , C40B20/04 , C40B30/10 , C40B50/16 , C40B50/18 , G01N33/53 , G01N33/543 , G01N33/573 , C12P
CPC分类号： G01N33/573 , B01J19/0046 , B01J2219/00454 , B01J2219/005 , B01J2219/00581 , B01J2219/00592 , B01J2219/00596 , B01J2219/0072 , C07B2200/11 , C40B20/04 , C40B30/10 , C40B40/04 , C40B50/16 , C40B50/18 , G01N2333/9121
摘要： The present invention provides a library of compounds, wherein each compound is encoded by several coding building blocks that are each separately attached to a solid support via a cleavable linker. Following screening of the compounds, the coding tags can be cleaved, and then characterized by mass spectrometry.
摘要翻译：本发明提供了一种化合物文库，其中每种化合物由几个编码构建单元编码，每个编码结构单元通过可切割连接体分别连接到固体支持物上。在筛选化合物之后，编码标签可以被切割，然后通过质谱法进行表征。

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