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11. 发明授权

US08270202B2 Programming non-volatile storage element using current from other element 有权
标题翻译：使用来自其他元素的电流编程非易失性存储元件
公开(公告)号：US08270202B2
公开(公告)日：2012-09-18
申请号：US13154832
申请日：2011-06-07
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： Control circuitry provides control signals to a common X line and a set of Y lines to change a first data storage element of the multiple data storage elements from a first state to a second state by passing a current into the first data storage element from a different Y line through a different storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines.
摘要翻译：控制电路向公共X线和一组Y线提供控制信号，以将多个数据存储元件的第一数据存储元件从第一状态改变到第二状态，通过将电流从不同的X线传送到第一数据存储元件 Y线通过不同的存储元件。控制电路向公共X线路和Y线组提供控制信号，以通过将电流从数据存储器传递到附加数据存储元件中来顺序地将多个数据存储元件的附加数据存储元件从第一状态改变到第二状态先前更改为第二状态的多个数据存储元素的元素及其相关的不同Y行。

12. 发明申请

US20120224409A1 THREE DIMENSIONAL MEMORY SYSTEM WITH PAGE OF DATA ACROSS WORD LINES 有权
标题翻译：三维存储器系统，具有数据线的数据
公开(公告)号：US20120224409A1
公开(公告)日：2012-09-06
申请号：US13039581
申请日：2011-03-03
申请人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
发明人： Tianhong Yan , Luca G. Fasoli , Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C8/10
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C2213/33 , G11C2213/35 , G11C2213/71
摘要： A three dimensional monolithic memory array of non-volatile storage elements includes a plurality of word lines and a plurality of bit lines. The plurality of bit lines are grouped into columns. One page of data is stored across multiple word lines by programming non-volatile storage elements connected to one column of bit lines and multiple word lines while maintaining the selection of the one column of bit lines. In one embodiment, programming non-volatile storage elements includes selectively connecting bit lines to sense amplifiers using selection circuits that include a storage device, a select circuit connected to the storage device and one or more level shifters providing two or more interfaces to the respective selection circuit.
摘要翻译：非易失性存储元件的三维单片存储器阵列包括多个字线和多个位线。多个位线被分组成列。通过编程连接到一列位线和多个字线的非易失性存储元件，同时保持对一列位线的选择，一页数据被存储在多个字线上。在一个实施例中，编程非易失性存储元件包括使用包括存储设备，连接到存储设备的选择电路和提供两个或更多个接口的各个选择的一个或多个电平移位器的选择电路选择性地将位线连接到读出放大器电路。

13. 发明授权

US08203864B2 Memory cell and methods of forming a memory cell comprising a carbon nanotube fabric element and a steering element 有权
标题翻译：存储单元和形成包含碳纳米管织物元件和转向元件的存储单元的方法
公开(公告)号：US08203864B2
公开(公告)日：2012-06-19
申请号：US13083746
申请日：2011-04-11
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L51/0048 , H01L51/0595 , Y10S977/742
摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.
摘要翻译：提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。还提供其他方面。

14. 发明申请

US20120147648A1 THREE DIMENSIONAL NON-VOLATILE STORAGE WITH DUAL GATE SELECTION OF VERTICAL BIT LINES 有权
标题翻译：具有双门选择垂直位线的三维非易失性存储
公开(公告)号：US20120147648A1
公开(公告)日：2012-06-14
申请号：US13323710
申请日：2011-12-12
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
摘要翻译：适用于响应于在其上施加电压差而可逆地改变电导水平的存储器元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

15. 发明申请

US20120147644A1 CONTINUOUS MESH THREE DIMENSIONAL NON-VOLATILE STORAGE WITH VERTICAL SELECT DEVICES 有权
标题翻译：连续三次三维非易失性存储与垂直选择器件
公开(公告)号：US20120147644A1
公开(公告)日：2012-06-14
申请号：US13323680
申请日：2011-12-12
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C5/02 , H01L21/336
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683
摘要： A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
摘要翻译：适用于响应于在其上施加电压差而可逆地改变电导水平的存储器元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。

16. 发明申请

US20120140546A1 Multi-Bit Resistance-Switching Memory Cell 有权
公开(公告)号：US20120140546A1
公开(公告)日：2012-06-07
申请号：US13396489
申请日：2012-02-14
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage apparatus comprises a set of Y lines, a set of X lines and a plurality of memory cells in communication with the set of X lines and the set of Y lines. Each memory cell of the plurality of memory cells includes a resistance element in a static resistance condition and two or more reversible resistance-switching elements. The resistance element in the static resistance condition and the two or more reversible resistance-switching elements are connected to different Y lines of the set of Y lines. The resistance element in the low resistance state and the two or more reversible resistance-switching elements are connected to a common X line of the set of X lines. One or multiple bits of data are programmed into a particular memory cell of the plurality of memory cells by causing current flow between Y lines connected to the particular memory cell.

17. 发明申请

US20120135580A1 Three-Dimensional Memory Structures Having Shared Pillar Memory Cells 有权
标题翻译：具有共享柱状记忆单元的三维记忆结构
公开(公告)号：US20120135580A1
公开(公告)日：2012-05-31
申请号：US13365991
申请日：2012-02-03
申请人： Roy E. Scheuerlein , Eliyahou Harari
发明人： Roy E. Scheuerlein , Eliyahou Harari
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/35 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.
摘要翻译：公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。共享支柱结构包括两个非易失性存储元件。每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。各个存储元件各自包括转向元件和状态改变元件。

18. 发明申请

US20120044733A1 Single Device Driver Circuit to Control Three-Dimensional Memory Element Array 有权
标题翻译：用于控制三维存储器元件阵列的单器件驱动器电路
公开(公告)号：US20120044733A1
公开(公告)日：2012-02-23
申请号：US12938028
申请日：2010-11-02
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C7/12 , H01L21/02 , G11C5/02
CPC分类号： G11C13/0026 , B82Y10/00 , G11C7/12 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/0038 , G11C13/025 , G11C17/165 , G11C2013/0073 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/0688
摘要： A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.
摘要翻译：存储器件包括耦合在位和字线之间的二极管加电阻率开关元件存储单元，单个器件位线驱动器，其栅极耦合到位线解码器控制引线，耦合到位线驱动器的源极/漏极以及耦合到位线，具有耦合到字线解码器控制引线的栅极的单器件字线驱动器，耦合到字线驱动器输出的源极/漏极以及耦合到字线的漏极/源极，耦合在位线和位线之间的第一泄放二极管第一泄放二极管控制器和耦合在字线和第二泄放二极管控制器之间的第二泄放二极管。第一泄放二极管控制器响应于位线解码器信号将第一泄放二极管连接到低电压。第二泄放二极管控制器响应于字线解码器信号将第二泄放二极管连接到高电压。

19. 发明授权

US08110863B2 TFT charge storage memory cell having high-mobility corrugated channel 有权
标题翻译：具有高迁移率波纹通道的TFT电荷存储单元
公开(公告)号：US08110863B2
公开(公告)日：2012-02-07
申请号：US11143355
申请日：2005-06-01
申请人： Roy E Scheuerlein
发明人： Roy E Scheuerlein
IPC分类号： H01L29/788
CPC分类号： H01L29/42332 , B82Y10/00 , G11C16/0475 , H01L21/845 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1211 , H01L29/0649 , H01L29/1037 , H01L29/66833 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/78618 , H01L29/7881 , H01L29/792
摘要： A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments, multiple memory levels are formed stacked above a single substrate.
摘要翻译：描述每个单元具有两个位的可重写非易失性存储单元。存储单元优选通过通过通道热电子注入方法将电荷存储在介电电荷存储层中或电隔离的导电纳米晶体中来进行操作。在优选实施例中，通道区域具有波纹形状，在两个存储区域之间提供额外的隔离。沟道区域被沉积并且优选地由多晶锗或硅 - 锗形成。本发明的存储单元可以形成在存储器阵列中; 在优选实施例中，在单个衬底上堆叠形成多个存储器级。

20. 发明授权

US08102698B2 Structure and method for biasing phase change memory array for reliable writing 失效
标题翻译：用于偏置相变存储器阵列以进行可靠写入的结构和方法
公开(公告)号：US08102698B2
公开(公告)日：2012-01-24
申请号：US12952944
申请日：2010-11-23
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/21 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481
摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
摘要翻译：具有包括二极管和相变材料的存储单元的存储器阵列通过将所有未选择的存储单元维持在反向偏置状态来可靠地编程。因此，泄漏低，并且确保没有未选择的存储器单元受到干扰。为了在顺序写入期间避免干扰未选择的存储单元，在选择新的位线和字线之前，先前选择的字线和位线被带到其未选择的电压。改进的电流镜结构控制相变材料的状态切换。

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