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11. 发明申请

US20080312346A1 Conversion of Lignocellulosic Biomass to Chemicals and Fuels 失效
标题翻译：将木质纤维素生物质转化为化学品和燃料
公开(公告)号：US20080312346A1
公开(公告)日：2008-12-18
申请号：US11763538
申请日：2007-06-15
申请人： Michael J. McCall , Robert J. Allen , David E. Mackowiak
发明人： Michael J. McCall , Robert J. Allen , David E. Mackowiak
IPC分类号： B01D17/05
CPC分类号： C10L5/44 , C10G1/083 , C10G1/086 , Y02E50/10 , Y02E50/30 , Y02P30/20
摘要： A method for preparing biomass for slurry processing. The method includes solubilizing the solid material into either a dissolved state or a suspended solid in a liquid phase, and treating the liquid phase to produce chemicals and fuels.
摘要翻译：一种用于制备浆料处理生物质的方法。该方法包括将固体物质溶解在溶解状态或液相中的悬浮固体，以及处理液相以产生化学品和燃料。

12. 发明申请

US20080311435A1 Gas diffusion electrodes, membrane-electrode assemblies and method for the production thereof 有权
标题翻译：气体扩散电极，膜 - 电极组件及其制造方法
公开(公告)号：US20080311435A1
公开(公告)日：2008-12-18
申请号：US12154499
申请日：2008-05-23
申请人： Andrea F. Gulla , Robert J. Allen , Emory De Castro , Enrico Ramunni
发明人： Andrea F. Gulla , Robert J. Allen , Emory De Castro , Enrico Ramunni
IPC分类号： H01M4/00
CPC分类号： H01M4/8867 , C23C14/022 , C23C14/14 , C23C14/32 , C25D3/50 , C25D5/006 , C25D7/0607 , H01M4/8605 , H01M4/8807 , H01M4/92 , H01M8/1004 , Y02P70/56 , Y10T29/49115
摘要： A gas diffusion electrode comprising an electrically conductive web, a non-catalyzed gas diffusion layer comprising at least one electroconductive filler and at least one binder, and a noble metal coating obtained by subjecting an electrically conductive web to a first ion beam having an energy not higher than 500 eV, then to a second beam having an energy of at least 500 eV, containing the ions of at least one noble metal.
摘要翻译：一种气体扩散电极，包括导电网，非催化气体扩散层，其包含至少一种导电填料和至少一种粘合剂，以及贵金属涂层，其通过使导电网经受第一离子束而获得，所述第一离子束具有不能高于500eV，然后到达具有至少500eV的能量的第二束，其含有至少一种贵金属的离子。

13. 发明申请

US20080235641A1 CRITICAL AREA COMPUTATION OF COMPOSITE FAULT MECHANISMS USING VORONOI DIAGRAMS 失效
标题翻译：使用VORONOI图形的复合故障机制的关键区域计算
公开(公告)号：US20080235641A1
公开(公告)日：2008-09-25
申请号：US12132714
申请日：2008-06-04
申请人： Robert J. Allen , Evanthia Papadopoulou , Mervyn Yee-Min Tan
发明人： Robert J. Allen , Evanthia Papadopoulou , Mervyn Yee-Min Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a composite Voronoi diagram based on the individual Voronoi diagrams. The invention computes the critical area for composite fault mechanisms of the integrated circuit design based on the composite Voronoi diagram.
摘要翻译：公开了一种在集成电路设计中确定与不同类型的故障机制相关联的关键区域的方法。本发明通过为单个故障机制的关键区域构建单独的Voronoi图和基于各个Voronoi图的复合Voronoi图来实现。本发明基于复合Voronoi图计算了集成电路设计复合故障机理的关键区域。

14. 发明申请

US20080168414A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING AND MODIFYING THE CRITICAL AREA OF AN INTEGRATED CIRCUIT DESIGN. 失效
标题翻译：用于显示和修改集成电路设计关键领域的方法，装置和计算机程序产品。
公开(公告)号：US20080168414A1
公开(公告)日：2008-07-10
申请号：US11620059
申请日：2007-01-05
申请人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
发明人： Robert J. Allen , Sarah C. Braasch , Matthew T. Guzowski , Jason D. Hibbeler , Daniel N. Maynard , Kevin W. McCullen , Evanthia Papadopoulou , Mervyn Y. Tan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.
摘要翻译：一种用于可视地指示有助于定义的关键区域图案的设计的一个或多个边缘之间的交互的方法，装置和计算机程序产品。

15. 发明授权

US07389480B2 Content based yield prediction of VLSI designs 有权
标题翻译：基于内容的VLSI设计的产量预测
公开(公告)号：US07389480B2
公开(公告)日：2008-06-17
申请号：US10908342
申请日：2005-05-09
申请人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
发明人： Robert J. Allen , Daria R. Dooling , Jason D. Hibbeler , Daniel N. Maynard , Sarah C. Prue , Ralph J. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.
摘要翻译：一种用于预测VLSI设计产量的系统，方法和程序产品。提供了一种方法，包括以下步骤：通过类型识别和分组集成电路设计中包含的子电路; 计算集成电路设计中区域的关键面积值; 以及基于用于计算临界面积值的区域的类型将不同的屈服模型应用于临界区域值，其中每个产量模型依赖于类型。

16. 发明申请

US20080127004A1 METHOD FOR COMPUTING THE CRITICAL AREA OF COMPOUND FAULT MECHANISMS 失效
标题翻译：计算化合物故障机理关键领域的方法
公开(公告)号：US20080127004A1
公开(公告)日：2008-05-29
申请号：US11461805
申请日：2006-08-02
申请人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
发明人： Robert J. Allen , Sarah C. Braasch , Mervyn Y. Tan
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed is a method of calculating critical area based on both independent and dependent compound fault mechanisms. This critical area is calculated by generating, for each simple fault mechanism in the compound fault mechanism, a map made up of polygonal regions, where values on a third dimensional z-axis represent the critical defect size for each single fault mechanism at a point x,y. These maps are overlaid and the planar faces (i.e., top surfaces) of each region of each map are projected onto the x,y plane in order to identify intersecting sub-regions. The dominant fault mechanism within each sub-region is identified based on an answer to predetermined Boolean expression and the critical areas for all of the sub-regions are accumulated in order to obtain the total critical area for the compound fault mechanism.
摘要翻译：公开了一种基于独立和依赖复合故障机制来计算临界面积的方法。该关键区域通过为复合故障机制中的每个简单故障机制产生由多边形区域组成的地图来计算，其中第三维z轴上的值表示在点x处的每个单个故障机制的临界缺陷尺寸，y。覆盖这些贴图，并且将每个贴图的每个区域的平面（即，顶面）投影到x，y平面上，以便识别相交的子区域。基于对预定布尔表达式的答案来识别每个子区域内的主要故障机制，并且累积所有子区域的临界区域以获得复合故障机制的总临界面积。

17. 发明授权

US07302651B2 Technology migration for integrated circuits with radical design restrictions 有权
标题翻译：具有激进设计限制的集成电路的技术迁移
公开(公告)号：US07302651B2
公开(公告)日：2007-11-27
申请号：US10904225
申请日：2004-10-29
申请人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
发明人： Robert J. Allen , Cam V. Endicott , Fook-Luen Heng , Jason D. Hibbeler , Kevin W. McCullen , Rani Narayan , Robert F. Walker , Xin Yuan
IPC分类号： G06F17/50 , G03F1/00 , G03C5/00 , G01R31/26
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

18. 发明授权

US06941528B2 Use of a layout-optimization tool to increase the yield and reliability of VLSI designs 失效
标题翻译：使用布局优化工具来提高VLSI设计的产出和可靠性
公开(公告)号：US06941528B2
公开(公告)日：2005-09-06
申请号：US10604962
申请日：2003-08-28
申请人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
发明人： Robert J. Allen , Jason D. Hibbeler , Gustavo E. Tellez
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.
摘要翻译：本发明提供了一种用于优化集成电路设计中的冗余通孔的布置的方法和结构。本发明首先通过确定哪些通孔没有冗余通孔来定位目标通孔。然后，本发明在目标通孔上或附近绘制标记物形状。标记形状仅在每个目标通孔的水平或垂直方向绘制。本发明同时将第一方向上的所有标记形状扩展到预定长度，或者直到标记形状达到接地规则的极限。在扩展期间，不同的标记形状将被扩展到不同的长度。本发明确定哪些标记形状被充分扩展以形成有效的冗余通路以产生第一组潜在的冗余通孔，并且本发明消除了不能充分扩展以形成有效的冗余通路的标记形状。

19. 发明授权

US06855660B2 Rhodium electrocatalyst and method of preparation 有权
标题翻译：铑电催化剂及其制备方法
公开(公告)号：US06855660B2
公开(公告)日：2005-02-15
申请号：US10141108
申请日：2002-05-08
申请人： Yu-Min Tsou , Hua Deng , Gian Nicola Martelli , Robert J. Allen , Emory S. De Castro
发明人： Yu-Min Tsou , Hua Deng , Gian Nicola Martelli , Robert J. Allen , Emory S. De Castro
IPC分类号： G01N33/48 , B01J27/045 , B01J37/20 , C25B11/08 , H01M4/86 , H01M4/88 , H01M4/92 , B01J27/02 , C25B11/00 , C25C1/02
CPC分类号： C25B11/0447 , B01J27/045 , C25B1/26 , H01M4/8605 , H01M4/881 , H01M4/8842 , H01M4/923
摘要： A rhodium sulfide electrocatalyst formed by heating an aqueous solution of rhodium salt until a steady state distribution of isomers is obtained and then sparging hydrogen sulfide into the solution to form the rhodium sulfide and a membrane electrode assembly with the said electrode and a process for electrolyzing hydrochloric acid.
摘要翻译：通过加热铑盐水溶液直到异构体的稳态分布形成的硫化铑电催化剂，然后将硫化氢喷射到溶液中以形成硫化铑，并且与所述电极和电解电解盐酸盐的方法酸。

20. 发明授权

US06651229B2 Generation of refined switching windows in static timing analysis 有权
标题翻译：在静态时序分析中生成精细的切换窗口
公开(公告)号：US06651229B2
公开(公告)日：2003-11-18
申请号：US09682707
申请日：2001-10-09
申请人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
发明人： Robert J. Allen , Ravishankar Arunachalam , David J. Hathaway
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A method and structure to determine timing windows in a static timing analysis of an integrated circuit design, determines for at least one node in the integrated circuit design, an initial set of sub-windows and merges the sub-windows of the initial set into a final set of sub-windows.
摘要翻译：在集成电路设计的静态时序分析中确定定时窗口的方法和结构，为集成电路设计中的至少一个节点确定初始的子窗口集合并将初始集合的子窗口合并为最后一套子窗口。

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