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11. 发明授权

US06377193B1 System for converting between non-logarithmic values and logarithmic values 有权
标题翻译：用于在非对数值和对数值之间进行转换的系统
公开(公告)号：US06377193B1
公开(公告)日：2002-04-23
申请号：US09514038
申请日：2000-02-25
申请人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
发明人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
IPC分类号： H03M750
CPC分类号： H03M7/3013 , G06F7/556
摘要： An audio signal processor for processing 1-bit signals, comprises an input 40 for receiving a 1-bit signal, means 41, 42 for applying a predetermined filter characteristic to the 1-bit signal whereby the signal is also converted to an n-bit signal where n is greater than one, means 43 for determining the absolute value of the n-bit signal, means 46, 51 for producing a dynamics control signal dependent on the said absolute value, means 48 for applying the dynamics control signal to the 1-bit input signal, and means 49 for requantizing the dynamics controlled signal as a 1-bit signal and shaping the noise in the requantized 1-bit signal. Circuits for producing LOG base 2 and the corresponding anti-log are also disclosed.
摘要翻译：用于处理1位信号的音频信号处理器包括用于接收1位信号的输入端40，用于对1位信号施加预定的滤波特性的装置41,42，由此信号也被转换成n位信号，其中n大于1，用于确定n位信号的绝对值的装置43，用于产生取决于所述绝对值的动力学控制信号的装置46,51，用于将动态控制信号施加到1 以及用于将动态控制信号重新量化为1比特信号并对重新量化的1比特信号中的噪声进行整形的装置49。还公开了用于生成LOG基础2的电路和相应的反对数。

12. 发明授权

US06286020B1 Signal processor delta-sigma modulator stage 失效
标题翻译：信号处理器delta-sigma调制器级
公开(公告)号：US06286020B1
公开(公告)日：2001-09-04
申请号：US08979761
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe , James Andrew Scott Angus
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe , James Andrew Scott Angus
IPC分类号： G06F1710
CPC分类号： H03M7/3006 , H03M7/3042
摘要： A 1-bit nth order Delta Sigma Modulator where n is at least one comprises a linear signal processing section (50) which processes the 1-bit signal and produces a p bit output, a filter (52) which filters the p bit signal, an adder (53) a quantizer Q coupled to the output of the adder (53) to quantize a p bit signal to a 1-bit output signal, and a noise shaping section 51 which feeds the 1-bit output signal back to the adder 53.
摘要翻译： 1位n阶ΔΣ调制器，其中n至少为1包括处理1位信号并产生ap位输出的线性信号处理部分（50），对P位信号进行滤波的滤波器（52）加法器（53）耦合到加法器（53）的输出的量化器Q，以将ap位信号量化到1位输出信号;以及噪声整形部分51，将1位输出信号反馈给加法器53。

13. 发明授权

US06281885B1 Audio processing 有权
标题翻译：音频处理
公开(公告)号：US06281885B1
公开(公告)日：2001-08-28
申请号：US09178333
申请日：1998-10-23
申请人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
发明人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
IPC分类号： G09G500
CPC分类号： G06F3/16 , G06F3/04847 , H04H60/04
摘要： Audio processing apparatus comprises an audio processor operable to apply one or more processing operations from a set of audio processing operations to an input audio signal; adjustment controls for adjusting processing parameters associated with each of the set of processing operations; a display screen for displaying icons representing each processing operation of the set of audio processing operations; and a detector for detecting user operation of the adjustment controls associated with an a processing operation and, in response to such a detection, for displacing the display position of the icon associated with that processing operation.
摘要翻译：音频处理装置包括音频处理器，可操作以将一个或多个处理操作从一组音频处理操作应用到输入音频信号; 用于调整与所述一组处理操作中的每一个相关联的处理参数的调整控制; 显示屏，用于显示表示所述一组音频处理操作的每个处理操作的图标; 以及检测器，用于检测与处理操作相关联的调节控制的用户操作，并且响应于这种检测，移动与该处理操作相关联的图标的显示位置。

14. 发明授权

US06188344B1 Signal processors 失效
标题翻译：信号处理器
公开(公告)号：US06188344B1
公开(公告)日：2001-02-13
申请号：US08979687
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： H03M300
CPC分类号： H03M7/3015
摘要： A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.
摘要翻译： 1位信号处理器接收具有第一采样率（例如64fs）的1比特信号。上变频器（41）将采样率提高到128 fs。一系列Delta Sigma调制器（42,43）处理信号。经处理的信号由转换器（44）下变频至64fs。至少ΔΣ调制器可以在集成电路上实现。下变换器被布置成防止噪声被折回到信号带中。

15. 发明授权

US6061007A 1-bit signal processing system 失效
标题翻译： 1位信号处理系统
公开(公告)号：US6061007A
公开(公告)日：2000-05-09
申请号：US979251
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： H03M7/00 , H03M7/42 , H03M3/00
CPC分类号： H03M7/3013 , H03M7/42
摘要： A 1-bit signal (44) is compressed (40, 41) by dividing it into a series of n-bit words and encoding the words according to the probability of their occurrence.
摘要翻译：通过将1比特信号（44,41）分成一系列n比特字来对其进行编码，并根据它们发生的概率进行编码。

16. 发明授权

US6020837A Signal processors 失效
标题翻译：信号处理器
公开(公告)号：US6020837A
公开(公告)日：2000-02-01
申请号：US979687
申请日：1997-11-26
申请人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
发明人： Peter Charles Eastty , Christopher Sleight , Peter Damien Thorpe
IPC分类号： H03M1/08 , H03M7/32 , H04B14/04 , H03M3/00
CPC分类号： H03M7/3015
摘要： A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.
摘要翻译： 1位信号处理器接收具有第一采样率（例如64fs）的1比特信号。上变频器（41）将采样率提高到128 fs。一系列Delta Sigma调制器（42,43）处理信号。经处理的信号由转换器（44）下变频至64fs。至少ΔΣ调制器可以在集成电路上实现。下变换器被布置成防止噪声被折回到信号带中。

17. 发明授权

US5712808A Digital signal processing 失效
公开(公告)号：US5712808A
公开(公告)日：1998-01-27
申请号：US510167
申请日：1995-08-02
申请人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
发明人： Peter Charles Eastty , Tetsuya Konishi , Conrad Charles Cooke
IPC分类号： G10L19/00 , G10H1/12 , H03H17/02 , H03H17/04 , G06F17/10
CPC分类号： G10H1/125 , H03H17/0294 , H03H17/04 , G10H2250/101 , G10H2250/121 , G10H2250/545
摘要： Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.

18. 发明申请

US20120177203A1 AUDIO NETWORK SYSTEM AND METHOD OF DETECTING TOPOLOGY IN AUDIO SIGNAL TRANSMITTING SYSTEM 有权
标题翻译：音频网络系统及其在音频信号传输系统中的拓扑检测方法
公开(公告)号：US20120177203A1
公开(公告)日：2012-07-12
申请号：US13423115
申请日：2012-03-16
申请人： Nathan Bentall , Peter Charles Eastty
发明人： Nathan Bentall , Peter Charles Eastty
IPC分类号： H04H20/88
CPC分类号： H04L45/00
摘要： In an audio network system constructed from a main node and a plurality of satellite nodes each having a plurality of ports, the main node generates and transmits a main packet including audio signals of a plurality of channels. Each satellite node selects one of the plurality of ports in turn, and confirms whether the main packet arrives at the selected port every predetermined period or not. When the main packet arrives at the selected port every predetermined period, the main packet is received via the port by continuing selection of the port. In the case where reception of the main packet is lost, one is selected from the plurality of ports in turn, the operation to confirm arrival of the main packet is restarted, and another port at which the main packet arrives at the present stage is automatically found.
摘要翻译：在由主节点和多个卫星节点构成的每个具有多个端口的音频网络系统中，主节点生成并发送包括多个信道的音频信号的主分组。每个卫星节点依次选择多个端口中的一个，并且每个预定的周期确认主分组是否到达所选择的端口。当主包每隔预定时间到达所选择的端口时，通过继续选择该端口，经由端口接收主包。在主分组的接收丢失的情况下，从多个端口依次选择一个，重新开始确认主分组的到达的操作，并且主分组在当前阶段到达的另一个端口是自动的发现。

19. 发明授权

US07003358B2 Audio signal processors 有权
标题翻译：音频信号处理器
公开(公告)号：US07003358B2
公开(公告)日：2006-02-21
申请号：US10621764
申请日：2003-07-17
申请人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
发明人： Peter Charles Eastty , Peter Damien Thorpe , Christopher Sleight
IPC分类号： G06F17/00
CPC分类号： G11B20/10527
摘要： An audio signal processor which modifies audio signal components outside the conventional audio frequency band. The processor includes a Delta Sigma Modulator (DSM) that receives a non-interpolated digital audio signal sampled at a frequency of at least 198 kHz.
摘要翻译：音频信号处理器，其修改常规音频频带外的音频信号分量。该处理器包括一个ΔΣ调制器（DSM），其接收以至少198kHz的频率采样的非内插数字音频信号。

20. 发明授权

US06744788B2 Multiplexing digital signals 失效
标题翻译：复用数字信号
公开(公告)号：US06744788B2
公开(公告)日：2004-06-01
申请号：US09400504
申请日：1999-09-21
申请人： Peter Charles Eastty
发明人： Peter Charles Eastty
IPC分类号： H04J302
CPC分类号： H04J3/1605 , H04H20/28 , H04L25/03866
摘要： Data transmission apparatus for multiplexing one or more channel data streams of equal, predetermined, data rate into a transmission data stream comprises: means for generating a control data stream of the same data rate as the channel data rate, in which first periodically repeating portions of the control data stream provide a synchronisation signal and second periodically repeating portions of the control data stream provide identification data specifying information about the channel data streams with reference to a predetermined ordering of the channel data streams; and means for multiplexing the control data stream with the one or more channel data streams in a cyclic pattern of equally-sized data portions so that a data portion from the control data stream is followed by data portions from each of the channel data streams according to the predetermined ordering of channel data streams.
摘要翻译：用于将一个或多个相等的，预定的数据速率的信道数据流复用到传输数据流中的数据传输装置包括：用于产生与信道数据速率相同的数据速率的控制数据流的装置，其中第一周期性重复部分所述控制数据流提供同步信号，并且参考所述信道数据流的预定顺序，所述控制数据流的第二周期性重复部分提供关于所述信道数据流的识别数据指定信息; 以及用于以等于大小的数据部分的循环模式将所述控制数据流与所述一个或多个信道数据流多路复用的装置，使得来自所述控制数据流的数据部分遵循来自每个所述信道数据流的数据部分，通道数据流的预定顺序。

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