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11. 发明申请

US20120117413A1 METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) 失效
标题翻译：方法和基础设施，用于在协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环复制仿真
公开(公告)号：US20120117413A1
公开(公告)日：2012-05-10
申请号：US12941834
申请日：2010-11-08
申请人： Sameh W. Asaad , Ralph E. Bellofatto , Bernard Brezzo , Charles L. Haymes , Mohit Kapur , Benjamin D. Parker , Thomas Roewer , Jose A. Tierno
发明人： Sameh W. Asaad , Ralph E. Bellofatto , Bernard Brezzo , Charles L. Haymes , Mohit Kapur , Benjamin D. Parker , Thomas Roewer , Jose A. Tierno
IPC分类号： G06F1/06 , G06F1/04
CPC分类号： G06F1/10 , G06F1/06 , G06F17/5027 , H03K19/17736
摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
摘要翻译：多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。控制模块耦合到多个目标现场可编程门阵列。平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。多个本地时钟控制状态机驻留在目标现场可编程门阵列中。本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。还提供了一种方法。

12. 发明授权

US08640070B2 Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) 失效
标题翻译：在一组协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环再现仿真的方法和基础设施，
公开(公告)号：US08640070B2
公开(公告)日：2014-01-28
申请号：US12941834
申请日：2010-11-08
申请人： Sameh W Asaad , Ralph E Bellofatto , Bernard Brezzo , Charles L Haymes , Mohit Kapur , Benjamin D Parker , Thomas Roewer , Jose A Tierno
发明人： Sameh W Asaad , Ralph E Bellofatto , Bernard Brezzo , Charles L Haymes , Mohit Kapur , Benjamin D Parker , Thomas Roewer , Jose A Tierno
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F1/06 , G06F17/5027 , H03K19/17736
摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
摘要翻译：多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。控制模块耦合到多个目标现场可编程门阵列。平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。多个本地时钟控制状态机驻留在目标现场可编程门阵列中。本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。还提供了一种方法。

13. 发明申请

US20130170525A1 WIRE LIKE LINK FOR CYCLE REPRODUCIBLE AND CYCLE ACCURATE HARDWARE ACCELERATOR 有权
标题翻译：绕线循环可循环硬件加速器
公开(公告)号：US20130170525A1
公开(公告)日：2013-07-04
申请号：US13342128
申请日：2012-01-02
申请人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
发明人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
IPC分类号： H04B1/38
CPC分类号： G06F17/5027
摘要： First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
摘要翻译：提供了第一和第二现场可编程门阵列，其实现要被仿真的电路设计的第一和第二块。现场可编程门阵列以第一时钟频率操作，并且提供线状链路以在它们之间发送多个信号。线状链路包括在第一现场可编程门阵列上串行化串行化多个信号的串行器; 第二现场可编程门阵列上的解串器，用于反序列化所述多个信号; 以及序列化器和解串器之间的连接。串行器和解串器以大于第一时钟频率的第二时钟频率操作，并且选择第二时钟频率使得多个信号的发送和接收的延迟小于对应于第一时钟频率的周期。

14. 发明授权

US07757142B2 Self-synchronizing pseudorandom bit sequence checker 失效
标题翻译：自同步伪随机比特序列检验器
公开(公告)号：US07757142B2
公开(公告)日：2010-07-13
申请号：US12174327
申请日：2008-07-16
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： H04L1/242
摘要： Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
摘要翻译：提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。在本发明的一个方面，PRBS检查技术包括以下步骤/操作。对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。然后，错误位的传播在后续的时钟周期被禁止。禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

15. 发明授权

US07724059B2 Clock scaling circuit 有权
标题翻译：时钟缩放电路
公开(公告)号：US07724059B2
公开(公告)日：2010-05-25
申请号：US10978183
申请日：2004-10-29
申请人： Mohit Kapur
发明人： Mohit Kapur
IPC分类号： G05F1/04 , H03K3/00
CPC分类号： G06F1/06 , G06F1/08
摘要： Techniques for scaling and switching clocks in a glitch-free manner are provided. For example, in one aspect of the present invention, a technique for switching a frequency associated with a master clock includes the following steps/operations. Two phase clocks are generated from a master clock, wherein the two phase clocks do not transition at substantially the same time. Then, one of the two phase clocks is used to create multiple frequencies by dividing the one phase clock, and the other phase clock is used to switch between the multiple frequencies of the one phase clock. Further, one of the two phase clocks may be in phase with the master clock and the other of the two phase clocks may be 180 degrees out of phase with the master clock such that they do not transition at the same time. Also, the two phase clocks may be non-overlapping.
摘要翻译：提供了以无毛刺方式缩放和切换时钟的技术。例如，在本发明的一个方面，用于切换与主时钟相关联的频率的技术包括以下步骤/操作。从主时钟产生两个相位时钟，其中两个相位时钟在基本相同的时间不转换。然后，通过划分一相时钟来使用两个相位时钟之一来产生多个频率，而另一个相位时钟用于在一个相位时钟的多个频率之间切换。此外，两个相位时钟中的一个可以与主时钟同相，并且两个相位时钟中的另一个可以与主时钟异相180度，使得它们不同时转换。另外，两相时钟可能是不重叠的。

16. 发明申请

US20080276139A1 Self-Synchronizing Pseudorandom Bit Sequence Checker 失效
标题翻译：自同步伪随机比特序列检测器
公开(公告)号：US20080276139A1
公开(公告)日：2008-11-06
申请号：US12174327
申请日：2008-07-16
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： H04L1/242
摘要： Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
摘要翻译：提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。在本发明的一个方面，PRBS检查技术包括以下步骤/操作。对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。然后，错误位的传播在后续的时钟周期被禁止。禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

17. 发明授权

US09230046B2 Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator 有权
标题翻译：生成一个周期准确的，循环可重复的基于FPGA的硬件加速器的时钟信号
公开(公告)号：US09230046B2
公开(公告)日：2016-01-05
申请号：US13435614
申请日：2012-03-30
申请人： Sameth W. Asaad , Mohit Kapur
发明人： Sameth W. Asaad , Mohit Kapur
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F9/455
摘要： A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于为用于模拟被测器件（DUT）的操作的循环精确的基于FPGA的硬件加速器生成时钟信号。在一个实施例中，DUT包括多个器件时钟，以多个频率和定义的频率比产生多个器件时钟信号; 并且FPG硬件加速器包括多个加速器时钟，产生多个加速器时钟信号以操作FPGA硬件加速器来模拟DUT的操作。在一个实施例中，DUT的操作被映射到FPGA硬件加速器，并且加速器时钟信号以多个频率和定义的多个器件时钟频率的频率比生成，以保持DUT和DUT之间的周期精度 FPGA硬件加速器。在一个实施例中，可以使用FPGA硬件加速器来控制多个设备时钟的频率。

18. 发明授权

US07412640B2 Self-synchronizing pseudorandom bit sequence checker 有权
标题翻译：自同步伪随机比特序列检验器
公开(公告)号：US07412640B2
公开(公告)日：2008-08-12
申请号：US10650222
申请日：2003-08-28
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： H04L1/242
摘要： Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
摘要翻译：提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。在本发明的一个方面，PRBS检查技术包括以下步骤/操作。对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。然后，错误位的传播在后续的时钟周期被禁止。禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

19. 发明申请

US20070038404A1 Testable digital delay line 审中-公开
标题翻译：可测数字延时线
公开(公告)号：US20070038404A1
公开(公告)日：2007-02-15
申请号：US11546165
申请日：2006-10-11
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G06F19/00
CPC分类号： G01R31/31725 , H03K2005/00039 , H03K2005/00156
摘要： A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.
摘要翻译：提供了使用XOR门作为延迟元件的可测试的数字延迟线。使用XOR门可以独立控制多路复用器的每个输入。通过测试输入可以实现每个延迟元件，多路复用器输入可以在测试期间分配任何值，从而为延迟线提供非常鲁棒的模式故障覆盖。异或门可由三个限流逆变器组成。参考电压发生器在源极电压，偏置电压和接地之间产生恒定电压。这些恒定电压决定通过限流逆变器的电流量。选择一组不同的参考电压可编程在限流逆变器中流动的不同电流。该可编程电流导致每个XOR门延迟元件引入可编程单位延迟。

20. 发明申请

US20060247880A1 Testable digital delay line 失效
标题翻译：可测数字延时线
公开(公告)号：US20060247880A1
公开(公告)日：2006-11-02
申请号：US11117924
申请日：2005-04-29
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G01R31/00
CPC分类号： G01R31/31725 , H03K2005/00039 , H03K2005/00156
摘要： A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.
摘要翻译：提供了使用XOR门作为延迟元件的可测试的数字延迟线。使用XOR门可以独立控制多路复用器的每个输入。通过测试输入可以实现每个延迟元件，多路复用器输入可以在测试期间分配任何值，从而为延迟线提供非常鲁棒的模式故障覆盖。异或门可由三个限流逆变器组成。参考电压发生器在源极电压，偏置电压和接地之间产生恒定电压。这些恒定电压决定通过限流逆变器的电流量。选择一组不同的参考电压可编程在限流逆变器中流动的不同电流。该可编程电流导致每个XOR门延迟元件引入可编程单位延迟。

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