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1. 发明授权

US08640070B2 Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) 失效
标题翻译：在一组协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环再现仿真的方法和基础设施，
公开(公告)号：US08640070B2
公开(公告)日：2014-01-28
申请号：US12941834
申请日：2010-11-08
申请人： Sameh W Asaad , Ralph E Bellofatto , Bernard Brezzo , Charles L Haymes , Mohit Kapur , Benjamin D Parker , Thomas Roewer , Jose A Tierno
发明人： Sameh W Asaad , Ralph E Bellofatto , Bernard Brezzo , Charles L Haymes , Mohit Kapur , Benjamin D Parker , Thomas Roewer , Jose A Tierno
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F1/06 , G06F17/5027 , H03K19/17736
摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
摘要翻译：多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。控制模块耦合到多个目标现场可编程门阵列。平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。多个本地时钟控制状态机驻留在目标现场可编程门阵列中。本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。还提供了一种方法。

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