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11. 发明授权

US08803535B2 Impedance mismatch detection circuit 有权
标题翻译：阻抗失配检测电路
公开(公告)号：US08803535B2
公开(公告)日：2014-08-12
申请号：US13171725
申请日：2011-06-29
申请人： Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： G01R27/26 , H03F3/45
CPC分类号： H03F3/45475 , H03F2203/45594
摘要： A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.
摘要翻译：用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值和第二信号。第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。

12. 发明申请

US20130342258A1 LOW POWER RECEIVER FOR IMPLEMENTING A HIGH VOLTAGE INTERFACE IMPLEMENTED WITH LOW VOLTAGE DEVICES 有权
标题翻译：用于实现低电压设备实现的高电压接口的低功率接收器
公开(公告)号：US20130342258A1
公开(公告)日：2013-12-26
申请号：US13530426
申请日：2012-06-22
申请人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译：一种包括第一级和第二级的装置。第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。第二级可以被配置为响应于第一电压而产生核心电压。从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。

13. 发明申请

US20120326745A1 Current-Mode Logic Buffer with Enhanced Output Swing 有权
标题翻译：具有增强输出摆幅的电流模式逻辑缓冲器
公开(公告)号：US20120326745A1
公开(公告)日：2012-12-27
申请号：US13165500
申请日：2011-06-21
申请人： Makeshwar Kothandaraman , Pankaj Kumar , Paul K. Hartley , John Christopher Kriz
发明人： Makeshwar Kothandaraman , Pankaj Kumar , Paul K. Hartley , John Christopher Kriz
IPC分类号： H03K19/003 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.
摘要翻译：具有增加的输出电压摆幅的差分缓冲电路包括至少包括第一和第二晶体管的差分输入级，第一和第二晶体管分别用于接收第一和第二信号。缓冲电路还包括连接在差分输入级与第一电压源之间的偏置级。偏置级用于产生作为提供给偏置级的第三信号的函数的静态电流。负载电路连接在第二电压源和差分输入级之间，缓冲电路的第一和第二差分输出在负载电路和差分输入级之间的结点处产生。负载电路分别包括与第一和第二晶体管耦合的第一和第二开关元件。当第一晶体管截止时，第一开关元件可操作以将第一差分输出电连接到第二电压源。当第二晶体管截止时，第二开关元件可操作以将第二差分输出电连接到第二电压源。

14. 发明授权

US08089739B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08089739B2
公开(公告)日：2012-01-03
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H3/22 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。第二电压供应节点可操作以接收小于第一电压的第二电压。第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

15. 发明申请

US20110102046A1 Interfacing between differing voltage level requirements in an integrated circuit system 审中-公开
标题翻译：集成电路系统中不同电压等级要求之间的接口
公开(公告)号：US20110102046A1
公开(公告)日：2011-05-05
申请号：US12610277
申请日：2009-10-31
申请人： PANKAJ KUMAR , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
发明人： PANKAJ KUMAR , Pramod Elamannu Parameswaran , Makeshwar Kothandaraman , Vani Deshpande , John Kriz
IPC分类号： H03L5/00
CPC分类号： H03K19/00315
摘要： A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
摘要翻译：一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内要与IO接口连接的IO内核设备。该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。

16. 发明授权

US07432762B2 Circuit having enhanced input signal range 有权
标题翻译：电路具有增强的输入信号范围
公开(公告)号：US07432762B2
公开(公告)日：2008-10-07
申请号：US11393171
申请日：2006-03-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03F3/45 , G06G7/12
CPC分类号： H03F3/45183 , H03F2200/513 , H03F2200/78 , H03F2203/45314 , H03F2203/45361 , H03F2203/45552 , H03F2203/45684
摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to generate a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors having a first threshold voltage associated therewith and being operative to receive the first and second signals, respectively, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and operative to receive the difference signal and to generate an output signal of the circuit that is indicative of the difference signal and is referenced to the supply voltage of the circuit.
摘要翻译：具有增强的输入信号范围的电路包括差分放大器，其操作以接收至少第一和第二信号，并在其输出处产生作为第一和第二信号之间的差的函数的差分信号。差分放大器包括具有至少第一和第二晶体管的输入级，其具有与其相关联的第一阈值电压，并且可分别接收第一和第二信号，并且负载包括至少第三和第四晶体管，其具有第二阈值电压相关联因此，第一阈值电压大于第二阈值电压。电路还包括耦合到差分放大器的输出级并且可操作地接收差分信号并产生指示差分信号的电路的输出信号并且参考电路的电源电压。

17. 发明申请

US20080238399A1 Buffer Circuit Having Multiplexed Voltage Level Translation 有权
标题翻译：具有复用电压电平转换的缓冲电路
公开(公告)号：US20080238399A1
公开(公告)日：2008-10-02
申请号：US11691590
申请日：2007-03-27
申请人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： G05F5/00
CPC分类号： H03K19/017581 , H03K19/01759
摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
摘要翻译：作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

18. 发明授权

US07430100B2 Buffer circuit with enhanced overvoltage protection 有权
标题翻译：具有增强型过压保护功能的缓冲电路
公开(公告)号：US07430100B2
公开(公告)日：2008-09-30
申请号：US11169139
申请日：2005-06-28
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H02H3/20
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
摘要翻译：具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。保护电路是可操作的：（i）当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时，将第一信号钳位到约第一电压电平; 和（ii）当第三信号小于或基本上等于第一电压电平时，产生基本上等于第三信号的第一信号。

19. 发明授权

US07248079B2 Differential buffer circuit with reduced output common mode variation 失效
公开(公告)号：US07248079B2
公开(公告)日：2007-07-24
申请号：US11285800
申请日：2005-11-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K19/0175
CPC分类号： H04L25/0276
摘要： A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

20. 发明授权

US07145364B2 Self-bypassing voltage level translator circuit 有权
标题翻译：自我旁路电压电平转换电路
公开(公告)号：US07145364B2
公开(公告)日：2006-12-05
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.
摘要翻译：响应于控制信号，电压电平转换器电路可选择性地以至少两种模式之一工作。在第一模式中，电压电平转换器电路用于将提供第一电压的参考第一源的输入信号转换为参考提供第二电压的第二源的输出信号。在第二模式中，电压电平转换器电路用于提供从电压转换器电路的输入到其输出的信号路径，而不转换输入信号。控制信号表示第一电压和第二电压之间的差。

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