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11. 发明申请

US20080087961A1 METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 有权
标题翻译：通过退火减少堆叠不良的方法
公开(公告)号：US20080087961A1
公开(公告)日：2008-04-17
申请号：US11548428
申请日：2006-10-11
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L27/092 , H01L21/8232
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

12. 发明授权

US08426265B2 Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
标题翻译：在栅极第一流中在CMOS电路中增长应变诱导材料的方法
公开(公告)号：US08426265B2
公开(公告)日：2013-04-23
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

13. 发明授权

US07622341B2 Sige channel epitaxial development for high-k PFET manufacturability 失效
标题翻译： Sige通道外延开发高k PFET可制造性
公开(公告)号：US07622341B2
公开(公告)日：2009-11-24
申请号：US12014815
申请日：2008-01-16
申请人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
发明人： Michael P. Chudzik , Dominic J. Schepis , Linda Black
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/823842 , H01L21/823878
摘要： A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.
摘要翻译：用于生长外延层的方法在衬底上图案掩模。掩模保护要形成N型场效应晶体管（NFET）的衬底的第一区域（N型区域），并露出衬底的第二区域（P型区域），其中P型场效应晶体管（PFET））将被形成。使用掩模，该方法可以仅在P型区域上外延生长硅锗层。然后去除掩模，并在N型区域和P型区域中对浅沟槽隔离（STI）沟槽进行图案化（使用不同的掩模）。该STI图案化工艺定位STI沟槽以便去除外延层的边缘。然后用隔离材料填充沟槽。最后，NFET形成为具有第一金属栅极，并且PFET形成为具有与第一金属栅极不同的第二金属栅极。第一金属门具有与第二金属门不同的功函数。

14. 发明申请

US20090152590A1 METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS 审中-公开
标题翻译：具有硅锗沉积物的半导体器件的方法和结构
公开(公告)号：US20090152590A1
公开(公告)日：2009-06-18
申请号：US11955488
申请日：2007-12-13
申请人： Thomas N. Adam , Linda Black , Huajie Chen , Dureseti Chidambarrao , Robert E. Davis , Judson R. Holt , Randolph F. Knarr , Christian Lavoie , Robert J. Purtell , Dominic J. Schepis
发明人： Thomas N. Adam , Linda Black , Huajie Chen , Dureseti Chidambarrao , Robert E. Davis , Judson R. Holt , Randolph F. Knarr , Christian Lavoie , Robert J. Purtell , Dominic J. Schepis
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636
摘要： A method of forming a semiconductor device including forming a second deposit of silicon-germanium on a first deposit of silicon-germanium, the first deposit formed in a conduction terminal region of a substrate of the semiconductor device and having a first percentage of germanium, and the second deposit having a second percentage of germanium that is less than the first percentage and supports forming a silicide deposit on the second deposit. A structure is also provided.
摘要翻译：一种形成半导体器件的方法，包括在硅 - 锗的第一沉积物上形成硅 - 锗的第二沉积物，所述第一沉积物形成在所述半导体器件的衬底的导电末端区域中并且具有第一百分比的锗，以及所述第二沉积物具有小于所述第一百分比的第二百分比的锗，并且在所述第二沉积物上支持形成硅化物沉积物。还提供了一种结构。

15. 发明授权

US08232186B2 Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure 失效
标题翻译：在PFET上对NFET和SiGe沟道反向eSiGe进行积分的方法及相关结构
公开(公告)号：US08232186B2
公开(公告)日：2012-07-31
申请号：US12128955
申请日：2008-05-29
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L21/20
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.
摘要翻译：公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。作为选择，PFET区域上的SiGe层可能变薄。

16. 发明授权

US07956417B2 Method of reducing stacking faults through annealing 失效
标题翻译：通过退火减少堆垛层错的方法
公开(公告)号：US07956417B2
公开(公告)日：2011-06-07
申请号：US12839588
申请日：2010-07-20
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

17. 发明授权

US07893493B2 Stacking fault reduction in epitaxially grown silicon 有权
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07893493B2
公开(公告)日：2011-02-22
申请号：US11456326
申请日：2006-07-10
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L27/12 , H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.
摘要翻译：中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中衬垫，其中外延生长的硅基本上是无层错的。

18. 发明授权

US07820501B2 Decoder for a stationary switch machine 有权
标题翻译：固定式开关机的解码器
公开(公告)号：US07820501B2
公开(公告)日：2010-10-26
申请号：US11548428
申请日：2006-10-11
申请人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
发明人： Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
摘要翻译：因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

19. 发明授权

US07674720B2 Stacking fault reduction in epitaxially grown silicon 失效
标题翻译：堆积外延生长硅中的断层减少
公开(公告)号：US07674720B2
公开(公告)日：2010-03-09
申请号：US12131214
申请日：2008-06-02
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

20. 发明授权

US07223662B2 Method of forming an epitaxial layer for raised drain and source regions by removing surface defects of the initial crystal surface 有权
标题翻译：通过去除初始晶体表面的表面缺陷来形成用于凸起的漏极和源极区的外延层的方法
公开(公告)号：US07223662B2
公开(公告)日：2007-05-29
申请号：US11082122
申请日：2005-03-16
申请人： Thorsten Kammler , Scott Luning , Linda Black
发明人： Thorsten Kammler , Scott Luning , Linda Black
IPC分类号： H01L21/336 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/26506 , H01L21/28035 , H01L29/41783 , H01L29/42384 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66772
摘要： By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.
摘要翻译：通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于可以显着减少生长的硅层和初始衬底表面。因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。

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