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11. 发明授权

US08183630B2 Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT 有权
标题翻译：具有集成在三维中并具有动态可调阈值电压VT的晶体管的电路
公开(公告)号：US08183630B2
公开(公告)日：2012-05-22
申请号：US12474851
申请日：2009-05-29
申请人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
发明人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
IPC分类号： H01L29/66 , H01L29/94
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.
摘要翻译：一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平处的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管包括与第二晶体管的沟道区相对的栅电极，第一晶体管和第二晶体管被绝缘区隔开，所述绝缘区由几种不同的介电材料构成，包括第一电介质材料和第二电介质材料。

12. 发明授权

US07972971B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium 有权
标题翻译：通过锗的缩合在同一衬底上生产Ge中具有不同含量的Si1-yGey基区的方法
公开(公告)号：US07972971B2
公开(公告)日：2011-07-05
申请号：US11761122
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3083 , H01L21/7624 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0
摘要翻译：本公开涉及一种用于生产包括具有不同的锗含量的多个Si1-yGey基半导电区（其中0

13. 发明授权

US07763915B2 Three-dimensional integrated C-MOS circuit and method for producing same 有权
标题翻译：三维集成C-MOS电路及其制造方法
公开(公告)号：US07763915B2
公开(公告)日：2010-07-27
申请号：US11654660
申请日：2007-01-18
申请人： Jean-Pierre Joly , Olivier Faynot , Laurent Clavelier
发明人： Jean-Pierre Joly , Olivier Faynot , Laurent Clavelier
IPC分类号： H01L29/80
CPC分类号： H01L27/0688 , H01L21/8221
摘要： The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.
摘要翻译：三维集成CMOS电路形成在混合基板中。在具有（100）取向的第一半导体硅层中，在底层形成n-MOS型晶体管，该层可以是张力应变的。在顶级，在具有（110）取向的锗的优选单晶和压缩应变的第二半导电层中形成p-MOS晶体管。第二半导电层被转移到其中预先形成n-MOS晶体管的第一块，然后形成p-MOS晶体管。

14. 发明申请

US20100155843A1 FIELD EFFECT TRANSISTOR WITH ALTERNATE ELECTRICAL CONTACTS 有权
标题翻译：具有替代电气接触的场效应晶体管
公开(公告)号：US20100155843A1
公开(公告)日：2010-06-24
申请号：US12665463
申请日：2008-06-19
申请人： Frederic Mayer , Laurent Clavelier , Thierry Poiroux , Gerard Billiot
发明人： Frederic Mayer , Laurent Clavelier , Thierry Poiroux , Gerard Billiot
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/7855 , H01L29/41791 , H01L29/66795
摘要： A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.
摘要翻译：一种场效应晶体管，包括：支撑层，基于半导体的多个有源区，每个有源区被配置为形成沟道并且布置在彼此相邻并连续的两个栅极之间，所述有源区和栅极被布置在支撑层，每个门包括在支撑层侧面的第一面和与第一面相对的第二面。两个栅极中的第一个的第二面电连接到在两个栅极中的第一个栅极的第二面上形成的第一电触点，并且两个栅极中的第二个的第一面电连接到第二电触点穿过支撑层。晶体管的栅极彼此不电连接。

15. 发明申请

US20090294822A1 CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT 有权
标题翻译：具有集成在三维尺寸并具有动态可调节阈值电压VT的晶体管的电路
公开(公告)号：US20090294822A1
公开(公告)日：2009-12-03
申请号：US12474851
申请日：2009-05-29
申请人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
发明人： Perrine Batude , Laurent Clavelier , Marie-Anne Jaud , Olivier Thomas , Maud Vinet
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.
摘要翻译：一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管包括与所述第二晶体管的沟道区相对的栅电极，所述第一晶体管和所述第二晶体管通过绝缘区隔开，所述绝缘区在所述第一晶体管的所述栅极和所述第一晶体管的所述沟道之间的第一区域中所述第二晶体管的组成和厚度设置成使得能够在所述第一晶体管的栅电极和所述第二晶体管的沟道之间的耦合，所述绝缘区包括所述第一区周围的第二区，以及第二晶体管的厚度和组成不同于所述第一区域的晶体管。

16. 发明申请

US20090017602A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE FOR MICROELECTRONICS AND OPTOELECTRONICS 有权
标题翻译：微电子和光电子半导体绝缘体衬底的制造方法
公开(公告)号：US20090017602A1
公开(公告)日：2009-01-15
申请号：US12144992
申请日：2008-06-24
申请人： Jean-Francois DAMLENCOURT , Laurent CLAVELIER
发明人： Jean-Francois DAMLENCOURT , Laurent CLAVELIER
IPC分类号： H01L21/00
CPC分类号： H01L21/02516 , H01L21/0242 , H01L21/02422 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/02639 , H01L21/02664
摘要： The method includes the following steps: supplying a substrate comprising a support having one face made of a dielectric material supporting a strained silicon thin layer having a or orientation, formation of a first mask on a portion of the strained silicon thin layer, epitaxy of Si1−xGex on the portion of the layer not masked by the first mask, germanium condensation, until a strained germanium layer is obtained, which rests on the face of the support made of a dielectric material, the strained germanium layer then being covered by a silicon oxide layer, elimination of the first mask and of the silicon oxide layer, formation of a second mask on said semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the remaining strained germanium portion and at least one region of the strained silicon portion, the second mask exposing a remaining strained germanium portion, epitaxial growth of germanium on the remaining strained germanium portion, in order to obtain a germanium thick layer, elimination of the second mask.
摘要翻译：该方法包括以下步骤：提供包括具有一个表面的支撑体的基底，该表面由电介质材料构成，该介电材料支撑具有<110>或<111>取向的应变硅薄层，在应变硅的一部分上形成第一掩模薄层，在未被第一掩模掩蔽的层的部分上的Si1-xGex的外延，锗缩合，直到获得应变锗层，其位于由介电材料制成的支撑体的表面上，应变锗层然后被氧化硅层覆盖，消除第一掩模和氧化硅层，在通过前一步骤暴露的所述半导体薄层上形成第二掩模，第二掩模保护剩余的应变锗的区域部分和应变硅部分的至少一个区域，第二掩模暴露剩余的应变锗部分，锗在剩余的应变锗上的外延生长为了获得锗厚层，消除了第二个掩模。

17. 发明申请

US20080220594A1 Fabrication method of a mixed substrate and use of the substrate for producing circuits 有权
标题翻译：混合基板的制造方法和用于制造电路的基板的使用
公开(公告)号：US20080220594A1
公开(公告)日：2008-09-11
申请号：US12071886
申请日：2008-02-27
申请人： Laurent Clavelier , Cyrille Le Royer , Jean-Francois Damlencourt
发明人： Laurent Clavelier , Cyrille Le Royer , Jean-Francois Damlencourt
IPC分类号： H01L21/321
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02694 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
摘要翻译：包括拉伸应变绝缘体上的部分和压电应变绝缘体上的部分的混合衬底的制造方法包括：第一步骤，制造在绝缘体上的应变基底衬底，其包括第一和第二拉伸应变硅区。在制造基底衬底之后，该方法包括以下连续步骤：掩蔽形成衬底的拉伸应变绝缘体上的部分的第一拉伸应变硅区，进行锗的第二拉伸应变硅区的锗富集处理从而形成压缩的应变锗层，形成所述压电应变绝缘体上的绝缘体上的部分，并且去除掩模。

18. 发明授权

US08866225B2 Field effect transistor with alternate electrical contacts 有权
标题翻译：具有交替电触点的场效应晶体管
公开(公告)号：US08866225B2
公开(公告)日：2014-10-21
申请号：US12665463
申请日：2008-06-19
申请人： Frederic Mayer , Laurent Clavelier , Thierry Poiroux , Gerard Billiot
发明人： Frederic Mayer , Laurent Clavelier , Thierry Poiroux , Gerard Billiot
IPC分类号： H01L27/12 , H01L29/78 , H01L29/66 , H01L29/417
CPC分类号： H01L29/7855 , H01L29/41791 , H01L29/66795
摘要： A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.
摘要翻译：一种场效应晶体管，包括：支撑层，基于半导体的多个有源区，每个有源区被配置为形成沟道并且布置在彼此相邻并连续的两个栅极之间，所述有源区和栅极被布置在支撑层，每个门包括在支撑层侧面的第一面和与第一面相对的第二面。两个栅极中的第一个的第二面电连接到在两个栅极中的第一个栅极的第二面上形成的第一电触点，并且两个栅极中的第二个的第一面电连接到第二电触点穿过支撑层。晶体管的栅极彼此不电连接。

19. 发明授权

US08501589B2 Method in the microelectronics fields of forming a monocrystalline layer 有权
标题翻译：微电子领域形成单晶层的方法
公开(公告)号：US08501589B2
公开(公告)日：2013-08-06
申请号：US13125951
申请日：2009-10-29
申请人： Franck Fournel , Thomas Signamarcheix , Laurent Clavelier , Chrystel Deguet
发明人： Franck Fournel , Thomas Signamarcheix , Laurent Clavelier , Chrystel Deguet
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02524 , H01L21/02538 , H01L21/02603 , H01L21/02667
摘要： A process for forming a thin film of a given material includes providing a first substrate having, on the surface, an amorphous and/or polycrystalline film of the given material and a second substrate is bonded to the first substrate by hydrophobic direct bonding (molecular adhesion), the second substrate having a single-crystal reference film of a given crystallographic orientation on the surface thereof. A heat treatment is applied at least to the amorphous and/or polycrystalline film, where the heat treatment causes at least a portion of the amorphous and/or polycrystalline film to undergo solid-phase recrystallization along the crystallographic orientation of the reference film, where the reference film acts as a recrystallization seed. The at least partly recrystallized film is then separated from at least a portion of the reference film.
摘要翻译：用于形成给定材料的薄膜的方法包括提供在表面上具有给定材料的非晶和/或多晶膜的第一基底，并且第二基底通过疏水直接键合（分子粘附），第二衬底具有在其表面上给定结晶取向的单晶参考膜。至少对非晶和/或多晶膜进行热处理，其中热处理使得至少一部分非晶和/或多晶膜沿着参考膜的结晶取向进行固相重结晶，其中参考膜用作再结晶种子。然后将至少部分重结晶的膜与参考膜的至少一部分分离。

20. 发明授权

US08288250B2 Method for transferring chips onto a substrate 有权
标题翻译：将芯片转移到基板上的方法
公开(公告)号：US08288250B2
公开(公告)日：2012-10-16
申请号：US12564597
申请日：2009-09-22
申请人： Laurent Clavelier , Chrystel Deguet , Patrick Leduc , Hubert Moriceau
发明人： Laurent Clavelier , Chrystel Deguet , Patrick Leduc , Hubert Moriceau
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/7813 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method for making a stack of at least two stages of circuits, each stage including a substrate and at least one component and metallic connections formed in or on this substrate, the assembly of a stage to be transferred onto a previous stage including: a) ionic implantation in the substrate of the stage to be transferred through at least part of the components, so as to form a weakened zone, b) formation of metallic connections of the components, c) transfer and assembly of some of this substrate onto the previous stage, and d) a step to thin the transferred part of the substrate by fracture along the weakened zone.
摘要翻译：一种用于制造至少两级电路的堆叠的方法，每个级包括衬底和形成在该衬底中或之上的至少一个部件和金属连接，待传送到前一级的级的组件，包括：a）通过至少部分组分转移到待转移阶段的衬底中的离子注入，以便形成弱化区，b）形成组分的金属连接，c）将该衬底中的一些衬底转移并组装到先前的阶段，以及d）通过沿着弱化区域的断裂来稀释基底的转移部分的步骤。

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