专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07972971B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium 有权
标题翻译：通过锗的缩合在同一衬底上生产Ge中具有不同含量的Si1-yGey基区的方法
公开(公告)号：US07972971B2
公开(公告)日：2011-07-05
申请号：US11761122
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3083 , H01L21/7624 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0
摘要翻译：本公开涉及一种用于生产包括具有不同的锗含量的多个Si1-yGey基半导电区（其中0

2. 发明授权

US07598145B2 Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium 有权
标题翻译：通过锗的缩合在同一基板上生产Ge中具有不同含量的Si1-yGey基区的方法
公开(公告)号：US07598145B2
公开(公告)日：2009-10-06
申请号：US11761074
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L21/336
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/84 , H01L27/1203 , H01L29/78684
摘要： A method for producing a microelectronic device comprising a plurality of Si1-yGey based semi-conductor zones (wherein 0
摘要翻译：一种微电子器件的制造方法，该微电子器件包括具有不同锗锗含量的多个Si 1-y Ga y基半导体区（其中0

3. 发明申请

US20070284625A1 METHOD FOR PRODUCING SI1-YGEY BASED ZONES WITH DIFFERENT CONTENTS IN GE ON A SAME SUBSTRATE BY CONDENSATION OF GERMANIUM 有权
标题翻译：通过对锗进行同位素生产在同一基片上的不同含量的SI1-YGEY基区的方法
公开(公告)号：US20070284625A1
公开(公告)日：2007-12-13
申请号：US11761122
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L23/58
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/3083 , H01L21/7624 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0
摘要翻译：本公开涉及一种用于生产包括多个基于Si 1-y基于半导电区（其中0

4. 发明申请

US20070287257A1 METHOD FOR PRODUCING SI1-YGEY BASED ZONES WITH DIFFERENT CONTENTS IN GE ON A SAME SUBSTRATE BY CONDENSATION OF GERMANIUM 有权
标题翻译：通过对锗进行同位素生产在同一基片上的不同含量的SI1-YGEY基区的方法
公开(公告)号：US20070287257A1
公开(公告)日：2007-12-13
申请号：US11761074
申请日：2007-06-11
申请人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Yves Morand , Laurent Clavelier
IPC分类号： H01L21/336
CPC分类号： H01L21/32105 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/84 , H01L27/1203 , H01L29/78684
摘要： The disclosure relates a method for producing a microelectronic device including a plurality of based Si1-yGey semi-conductor zones (where 0
摘要翻译：本公开内容涉及一种用于生产包括多个基于Si 1-y N y Y y半导体区（其中0 半导体层（其中0

5. 发明授权

US07989327B2 Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step 有权
标题翻译：一种半导体绝缘体衬底的制造方法，包括局部富锗步骤
公开(公告)号：US07989327B2
公开(公告)日：2011-08-02
申请号：US12340839
申请日：2008-12-22
申请人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
发明人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
IPC分类号： H01L21/20
CPC分类号： H01L21/32105 , H01L21/7624
摘要： A method of manufacturing a semi-conductor on insulator substrate from an SOI substrate, wherein a Si1-xGex layer is formed on a superficial layer of silicon having a buried electrical insulating layer. A silicon oxide layer is formed on the Si1-xGex layer. The resulting stack of silicon, Si1-xGex and silicon oxide layers is etched up to the buried insulating layer leaving an island of the stack, or up to the superficial layer leaving a zone of silicon and an island of the stack. A mask is formed to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island. The germanium of the Si1-xGex layer is condensed on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the insulating layer, with a silicon oxide layer on top of it.
摘要翻译：一种从SOI衬底制造绝缘体上半导体衬底的方法，其中在具有掩埋电绝缘层的硅的表面层上形成Si1-xGex层。在Si1-xGex层上形成氧化硅层。所得到的硅叠层Si1-xGex和氧化硅层被蚀刻到掩埋绝缘层上，留下堆叠的岛，或直到离开硅区域和堆叠岛的表层。形成掩模以防止在蚀刻结构上的氧化，其中保护掩模仅使岛的氧化硅层可见。 Si1-xGex层的锗在岛上被冷凝，以获得在绝缘层上富含锗或甚至一层锗的层，其上面具有氧化硅层。

6. 发明申请

US20080220594A1 Fabrication method of a mixed substrate and use of the substrate for producing circuits 有权
标题翻译：混合基板的制造方法和用于制造电路的基板的使用
公开(公告)号：US20080220594A1
公开(公告)日：2008-09-11
申请号：US12071886
申请日：2008-02-27
申请人： Laurent Clavelier , Cyrille Le Royer , Jean-Francois Damlencourt
发明人： Laurent Clavelier , Cyrille Le Royer , Jean-Francois Damlencourt
IPC分类号： H01L21/321
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02694 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.
摘要翻译：包括拉伸应变绝缘体上的部分和压电应变绝缘体上的部分的混合衬底的制造方法包括：第一步骤，制造在绝缘体上的应变基底衬底，其包括第一和第二拉伸应变硅区。在制造基底衬底之后，该方法包括以下连续步骤：掩蔽形成衬底的拉伸应变绝缘体上的部分的第一拉伸应变硅区，进行锗的第二拉伸应变硅区的锗富集处理从而形成压缩的应变锗层，形成所述压电应变绝缘体上的绝缘体上的部分，并且去除掩模。

7. 发明授权

US07648893B2 Method for manufacturing a semiconductor-on-insulator substrate for microelectronics and optoelectronics 有权
标题翻译：用于制造微电子学和光电子学的绝缘体上半导体衬底的方法
公开(公告)号：US07648893B2
公开(公告)日：2010-01-19
申请号：US12144992
申请日：2008-06-24
申请人： Jean-Francois Damlencourt , Laurent Clavelier
发明人： Jean-Francois Damlencourt , Laurent Clavelier
IPC分类号： H01L21/36
CPC分类号： H01L21/02516 , H01L21/0242 , H01L21/02422 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/02639 , H01L21/02664
摘要： A method for manufacturing a semiconductor including the steps of supplying a substrate having a support with one face supporting a strained silicon thin layer; forming a first mask on a portion of the strained silicon thin layer; epitaxy of Si1-xGex on the portion of the layer not masked by the first mask; condensating germanium to obtain a strained germanium layer, the strained germanium layer then covered by a silicon oxide layer; eliminating the first mask and of the silicon oxide layer thereby exposing a semi-conducting thin layer; forming a second mask on the semi-conducting thin layer exposed via the previous step, the second mask protecting a region of the exposing a remaining strained germanium portion; epitaxial growing germanium on the remaining strained germanium portion; and removing the second mask.
摘要翻译：一种制造半导体的方法，包括以下步骤：将具有支撑体的支撑体的基板供给支撑应变硅薄层的步骤; 在应变硅薄层的一部分上形成第一掩模; Si1-xGex在未被第一掩模掩蔽的部分上的外延; 冷凝锗以获得应变锗层，然后应变锗层被氧化硅层覆盖; 消除第一掩模和氧化硅层从而暴露半导体薄层; 在经由前述步骤暴露的半导电薄层上形成第二掩模，所述第二掩模保护暴露剩余的应变锗部分的区域; 在剩余的锗锗部分上外延生长锗; 并移除第二掩模。

8. 发明申请

US20090170295A1 MANUFACTURING METHOD FOR A SEMI-CONDUCTOR ON INSULATOR SUBSTRATE COMPRISING A LOCALISED Ge ENRICHED STEP 有权
标题翻译：一种半导体制造方法，该绝缘体基板包含一个本地化的加固步骤
公开(公告)号：US20090170295A1
公开(公告)日：2009-07-02
申请号：US12340839
申请日：2008-12-22
申请人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
发明人： Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
IPC分类号： H01L21/20
CPC分类号： H01L21/32105 , H01L21/7624
摘要： The invention relates to a manufacturing method of a semi-conductor on insulator substrate from an SOI substrate comprising a surface layer of silicon on an electrically insulating layer, called buried insulating layer, wherein a layer of Si1-xGex is formed on the superficial layer of silicon.The method comprises the following steps: formation of a silicon oxide layer on the layer of Si1-xGex, formation of a silicon oxide layer on the layer of Si1-xGex, etching of the stack formed by the superficial layer of silicon, the layer of Si1-xGex and the silicon oxide layer, wherein the etching is carried out either up to the buried insulating layer to obtain an etched structure with at least one island of said stack, or up to the superficial layer of silicon to obtain an etched structure with at least one zone of silicon and at least one island of said stack, formation of a mask to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island, condensation of the germanium of the layer of Si1-xGex on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the buried insulating layer, with a silicon oxide layer on top of it.
摘要翻译：本发明涉及一种绝缘体上半导体衬底的制造方法，该SOI衬底包括在绝缘层上称为掩埋绝缘层的硅表面层，其中Si1-xGex层形成在表面层上硅。该方法包括以下步骤：在Si1-xGex层上形成氧化硅层，在Si1-xGex层上形成氧化硅层，蚀刻由硅表面层形成的叠层 Si1-xGex和氧化硅层，其中蚀刻直到埋入绝缘层进行，以获得具有至少一个所述堆叠的岛的蚀刻结构，或直到硅的表面层，以获得具有硅的至少一个区域和所述堆叠的至少一个岛，形成掩模以防止在蚀刻结构上的氧化，其中所述保护掩模仅使所述岛的氧化硅层可见，所述层的锗的冷凝的Si1-xGex，以在掩埋绝缘层上形成富含锗或甚至一层锗的层，其上面具有氧化硅层。

9. 发明授权

US07625811B2 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures 有权
标题翻译：用于制造不同的第一和第二有源半导体区的方法及其用于制造C-MOS结构的方法
公开(公告)号：US07625811B2
公开(公告)日：2009-12-01
申请号：US11584635
申请日：2006-10-23
申请人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
发明人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
IPC分类号： H01L21/20 , H01L21/36 , H01L21/8238
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.
摘要翻译：根据本发明的方法使得能够在支撑体的前表面上产生第一和第二活性区域，所述区域分别由彼此不同的优选具有相同晶体结构的第一和第二单晶半导体材料形成。第一和第二活动区域的前表面也具有处于同一平面上的优点。这种方法特别在于通过第二半导体材料以单晶形式的结晶步骤从多晶和/或无定形形式的第二半导体材料制成的图案和由所述图案之间的界面区域产生第二活性区域和预选的第一活动区域。此外，通过堆叠基板和电绝缘薄层形成支撑体，电绝缘薄层的前表面形成支撑体的前表面。

10. 发明申请

US20070105315A1 Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures 有权
标题翻译：用于制造不同的第一和第二有源半导体区的方法及其用于制造C-MOS结构的方法
公开(公告)号：US20070105315A1
公开(公告)日：2007-05-10
申请号：US11584635
申请日：2006-10-23
申请人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
发明人： Jean-Charles Barbe , Laurent Clavelier , Benoit Vianay , Yves Morand
IPC分类号： H01L21/336
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/2022 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.
摘要翻译：根据本发明的方法使得能够在支撑体的前表面上产生第一和第二活性区域，所述区域分别由彼此不同的优选具有相同晶体结构的第一和第二单晶半导体材料形成。第一和第二活动区域的前表面也具有处于同一平面上的优点。这种方法特别在于通过第二半导体材料以单晶形式的结晶步骤从多晶和/或无定形形式的第二半导体材料制成的图案和由所述图案之间的界面区域产生第二活性区域和预选的第一活动区域。此外，通过堆叠基板和电绝缘薄层形成支撑体，电绝缘薄层的前表面形成支撑体的前表面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式