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11. 发明申请

US20120224415A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20120224415A1
公开(公告)日：2012-09-06
申请号：US13472514
申请日：2012-05-16
申请人： Jörg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jörg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： G11C11/412 , H01L21/265
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.
摘要翻译：本发明的一个或多个实施例涉及一种方法，包括：处理静态随机存取存储器单元中的第一n沟道存取晶体管的鳍以具有比第一n沟道下拉的鳍更低的载流子迁移率晶体管在存储单元中的第一反相器中，第一n沟道存取晶体管耦合在第一反相器的第一位线和第一节点之间; 以及处理所述存储单元中的第二n沟道存取晶体管的鳍以具有比所述存储单元中的第二反相器中的第二n沟道下拉晶体管的鳍更低的电荷载流子迁移率，所述第二n沟道存取晶体管耦合在第二反相器的第二位线和第二节点之间。

12. 发明申请

US20120223396A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20120223396A1
公开(公告)日：2012-09-06
申请号：US13472515
申请日：2012-05-16
申请人： Jörg BERTHOLD , Christian PACHA , Klaus VON ARNIM
发明人： Jörg BERTHOLD , Christian PACHA , Klaus VON ARNIM
IPC分类号： H01L27/088
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一个或多个实施例涉及一种装置，包括：第一晶体管，包括鳍片; 以及包括鳍的第二晶体管，所述第一晶体管的鳍具有比所述第二晶体管的鳍更低的载流子迁移率。

13. 发明申请

US20100308418A1 Semiconductor Devices and Methods of Manufacture Thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100308418A1
公开(公告)日：2010-12-09
申请号：US12481373
申请日：2009-06-09
申请人： Knut Stahrenberg , Roland Hampp , Jin-Ping Han , Klaus von Arnim
发明人： Knut Stahrenberg , Roland Hampp , Jin-Ping Han , Klaus von Arnim
IPC分类号： H01L27/088 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a gate dielectric and a cap layer disposed over the gate dielectric. The first transistor includes a gate including a metal layer disposed over the cap layer and a semiconductive material disposed over the metal layer. The semiconductor device includes a second transistor in a second region of the workpiece, which includes the gate dielectric and the cap layer disposed over the gate dielectric. The second transistor includes a gate that includes the metal layer disposed over the cap layer and the semiconductive material disposed over the metal layer. A thickness of the metal layer, a thickness of the semiconductive material, an implantation region of a channel region, or a doped region of the gate dielectric of the first transistor achieves a predetermined threshold voltage for the first transistor.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有栅极电介质的第一晶体管和设置在栅极电介质上的覆盖层。第一晶体管包括包括设置在盖层上的金属层的栅极和设置在金属层上的半导体材料。半导体器件包括在工件的第二区域中的第二晶体管，其包括设置在栅极电介质上的栅极电介质和盖层。第二晶体管包括栅极，其包括设置在覆盖层上的金属层和设置在金属层上的半导体材料。第一晶体管的金属层的厚度，半导体材料的厚度，沟道区的注入区域或栅极电介质的掺杂区域实现了第一晶体管的预定阈值电压。

14. 发明申请

US20100176479A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100176479A1
公开(公告)日：2010-07-15
申请号：US12354480
申请日：2009-01-15
申请人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
发明人： Sergei Postnikov , Thomas Schulz , Hans-Joachim Barth , Klaus von Arnim
IPC分类号： H01L29/68 , H01L21/762
CPC分类号： H01L27/11 , G03F7/40 , G03F7/7035 , H01L21/32139
摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.
摘要翻译：一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有初始宽度。该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

15. 发明申请

US20080308850A1 TRANSISTOR WITH REDUCED CHARGE CARRIER MOBILITY AND ASSOCIATED METHODS 有权
标题翻译：具有减少充电载波移动性和相关方法的晶体管
公开(公告)号：US20080308850A1
公开(公告)日：2008-12-18
申请号：US11764500
申请日：2007-06-18
申请人： Jorg Berthold , Christian Pacha , Klaus von Arnim
发明人： Jorg Berthold , Christian Pacha , Klaus von Arnim
IPC分类号： H01L29/76 , G11C11/34 , H01L21/425
CPC分类号： G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/785
摘要： A device includes a first transistor including a fin and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor. In a method, the fin of the first transistor is treated to have a lower charge carrier mobility than the fin of the second transistor.
摘要翻译：一种器件包括：第一晶体管，包括鳍片和包括鳍片的第二晶体管，第一晶体管的鳍片具有比第二晶体管鳍片更低的载流子迁移率。在一种方法中，第一晶体管的鳍被处理为具有比第二晶体管的鳍更低的载流子迁移率。

16. 发明申请

US20120154962A1 ELECTROSTATIC DISCHARGE CLAMPING DEVICES WITH TRACING CIRCUITRY 有权
标题翻译：具有跟踪电路的静电放电钳位装置
公开(公告)号：US20120154962A1
公开(公告)日：2012-06-21
申请号：US12975210
申请日：2010-12-21
申请人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
发明人： Christian Russ , Wolfgang Soldner , Klaus von Arnim , David Alvarez , Krzysztof Domanski , Gernot Langguth
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0285
摘要： Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.
摘要翻译：描述对应于具有跟踪电路的静电放电钳位电路的技术和架构。

17. 发明授权

US07482663B2 Semiconductor circuit arrangement 有权
标题翻译：半导体电路布置
公开(公告)号：US07482663B2
公开(公告)日：2009-01-27
申请号：US11653770
申请日：2007-01-16
申请人： Gerhard Knoblinger , Klaus Von Arnim
发明人： Gerhard Knoblinger , Klaus Von Arnim
IPC分类号： H01L29/76
CPC分类号： H01L27/088 , H01L27/0207
摘要： A semiconductor circuit arrangement includes at least one first and a second field effect transistor, where the field effect respectively have at least two active regions with, respectively, a source region, a drain region and an intermediate channel region, the surface of the channel regions having a gate formed on it, insulated by a gate dielectric, for actuating the channeel regions. At least one active region of the second field effect transistor is arranged between the at least two active regions of the first field effect transistor, which results in a reduced mismatch between the two transistors, caused by temperature and local distances.
摘要翻译：半导体电路装置包括至少一个第一和第二场效应晶体管，其中场效应分别具有至少两个有源区，分别具有源极区，漏极区和中间沟道区，沟道区的表面具有形成在其上的栅极，由栅极电介质绝缘，用于致动通道区域。第二场效应晶体管的至少一个有源区域被布置在第一场效应晶体管的至少两个有源区之间，这导致由温度和局部距离引起的两个晶体管之间的失配减小。

18. 发明授权

US07342421B2 CMOS circuit arrangement 有权
标题翻译： CMOS电路布置
公开(公告)号：US07342421B2
公开(公告)日：2008-03-11
申请号：US10573362
申请日：2004-09-17
申请人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
发明人： Jörg Berthold , Ralf Brederlow , Christian Pacha , Klaus Von Arnim
IPC分类号： H03K19/096 , H03K19/20
CPC分类号： H03K19/01728 , H01L2924/0002 , H03K19/0963 , H01L2924/00
摘要： In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit. At least a portion of the NMOS field effect transistors of the NMOS logic circuit have a first threshold voltage and at least a portion of the PMOS field effect transistors of the PMOS logic circuit have a third threshold voltage. The first clock transistor has a second threshold voltage. The first threshold voltage is lower than the second threshold voltage.
摘要翻译：在本发明的实施例中，提供了一种CMOS电路装置。 CMOS电路装置包括提供具有PMOS场效应晶体管的逻辑功能的PMOS逻辑电路，其中第一工作电位被馈送到PMOS逻辑电路的输入，提供逻辑功能的NMOS逻辑电路，具有NMOS场效应晶体管，第一时钟晶体管，其第一源极/漏极端子耦合到NMOS逻辑电路的输入，其中时钟信号被施加到第一时钟晶体管的栅极端子，并且其中第二工作电位被馈送到第二源极/漏极端子。 PMOS逻辑电路的输出和NMOS逻辑电路的输出彼此耦合。此外，逆变器电路耦合到PMOS逻辑电路的输出端和NMOS逻辑电路的输出。 NMOS逻辑电路的NMOS场效应晶体管的至少一部分具有第一阈值电压，PMOS逻辑电路的PMOS场效应晶体管的至少一部分具有第三阈值电压。第一时钟晶体管具有第二阈值电压。第一阈值电压低于第二阈值电压。

19. 发明申请

US20070284576A1 SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION 审中-公开
标题翻译：半导体电路布置及相关的温度检测方法
公开(公告)号：US20070284576A1
公开(公告)日：2007-12-13
申请号：US11689886
申请日：2007-03-22
申请人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
发明人： Christian Pacha , Thomas Schulz , Klaus Von Arnim
IPC分类号： H01L25/07 , H01L21/66
CPC分类号： G01K7/015 , H01L27/0727 , H01L27/1203 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.
摘要翻译：公开了半导体电路装置和温度检测方法。一个实施例包括半导体衬底，其上形成有由第二绝缘层横向界定的第一绝缘层和其上的薄的有源半导体区域。在有源半导体区域中，在第一绝缘层的表面上形成第一和第二掺杂区，用于定义沟道区，其中在沟道区的表面形成栅极电介质，并且在其上形成控制电极实现场效应晶体管。在有源半导体区域中，在第一绝缘层的表面上形成二极管掺杂区，该区通过具有第一或第二掺杂区的二极管侧区实现测量二极管，并且在其另外的第二绝缘层处限定第二绝缘层边区。

20. 发明申请

US20140002161A1 CIRCUIT ARRANGEMENT, A RETENTION FLIP-FLOP, AND METHODS FOR OPERATING A CIRCUIT ARRANGEMENT AND A RETENTION FLIP-FLOP 审中-公开
标题翻译：电路布置，保持性FLOP-FLOP以及操作电路布置和保持FLIP-FLOP的方法
公开(公告)号：US20140002161A1
公开(公告)日：2014-01-02
申请号：US13834400
申请日：2013-03-15
申请人： Klaus von Arnim , Stefan Bergler
发明人： Klaus von Arnim , Stefan Bergler
IPC分类号： H03K3/012 , H03K3/36
CPC分类号： H03K3/012 , H03K3/356156 , H03K3/35625 , H03K3/36
摘要： Various aspects of this disclosure provide a circuit arrangement, including: an input; a first latch circuit coupled to the input, the first latch circuit including a first forward inverter and a first feedback inverter; a switch, wherein a first terminal of the switch is coupled to an output of the first forward inverter; a second latch circuit coupled to a second terminal of the switch; an output coupled to the second latch circuit; and an isolating circuit configured to isolate the first forward inverter from an input of the first feedback inverter.
摘要翻译：本公开的各个方面提供一种电路装置，包括：输入端; 耦合到所述输入端的第一锁存电路，所述第一锁存电路包括第一正向反相器和第一反馈反相器; 开关，其中所述开关的第一端子耦合到所述第一正向逆变器的输出; 耦合到所述开关的第二端子的第二锁存电路; 耦合到所述第二锁存电路的输出; 以及隔离电路，被配置为将第一正向逆变器与第一反馈逆变器的输入隔离。

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