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11. 发明申请

US20080052470A1 RUNTIME REGISTER ALLOCATOR 失效
公开(公告)号：US20080052470A1
公开(公告)日：2008-02-28
申请号：US11929879
申请日：2007-10-30
申请人： Kartik Agaram , Marc Auslander , Kemal Ebcioglu
发明人： Kartik Agaram , Marc Auslander , Kemal Ebcioglu
IPC分类号： G06F12/08
CPC分类号： G06F9/383 , G06F9/3832 , G06F12/0862
摘要： Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

12. 发明申请

US20080046654A1 RUNTIME REGISTER ALLOCATOR 失效
标题翻译：运行注册分配器
公开(公告)号：US20080046654A1
公开(公告)日：2008-02-21
申请号：US11925015
申请日：2007-10-26
申请人： Kartik Agaram , Marc Auslander , Kemal Ebcioglu
发明人： Kartik Agaram , Marc Auslander , Kemal Ebcioglu
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3832 , G06F12/0862
摘要： Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.
摘要翻译：访问存储结构的方法和布置。包括用于提供存储访问指令的装置，用于响应于存储访问指令将地址输入存储结构数据高速缓存的布置，用于扩展具有预测寄存器号字段的存储访问指令的布置，预测寄存器号字段包含对应于与存储访问指令相关联的加载/存储操作数的推测位置的预测寄存器编号，用于通过扩展装置扩展的存储访问指令来推测访问存储结构的布置，以及用于恢复到布置如果加载/存储操作数不在投机位置，则输入地址。

13. 发明授权

US5799179A Handling of exceptions in speculative instructions 失效
标题翻译：在投机指示中处理例外
公开(公告)号：US5799179A
公开(公告)日：1998-08-25
申请号：US377563
申请日：1995-01-24
申请人： Kemal Ebcioglu , Gabriel Mauricio Silberman
发明人： Kemal Ebcioglu , Gabriel Mauricio Silberman
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3842 , G06F9/3863
摘要： CPU overhead is minimized through tracking speculative exceptions (202) for later processing during exception resolution (204) including pointing to the addresses of these speculative instructions, and resolving (204) these exceptions by correcting (206) what caused the exception and re-executing (208) the instructions which are known to be in a taken path. Tracking speculative exceptions has two components which use an exception bit which is set in response to an exception condition (213). The invention tracks an original speculative exception which occurs when a speculative instruction whose operand(s) do not have any exception bits set encounters an exception condition. Speculative exception resolution is triggered when a non-speculative instruction--which is in the taken path of a conditional branch--uses an operand from a register having its exception bit set. The presence of an exception condition and a non-speculative instruction yields an exception signal (220) to exception resolution (204). Speculative exception resolution (204) includes responding to output signals from the extra register and extra exception bit for correcting (204) the exception condition which caused the exception and re-executing (208) the instructions which depended on the results of the instructions causing the speculative exception. This invention also handles the case where a speculative instruction attempts to use a register having its exception bit set as above.
摘要翻译：通过跟踪推测异常（202）来最小化CPU开销，用于在异常解决（204）期间进行后续处理，包括指向这些推测性指令的地址，以及通过校正（206）导致异常和重新执行的原因来解决（204）这些异常（208）已知在采取路径中的指令。跟踪推测异常有两个组件，它们使用响应异常条件设置的异常位（213）。本发明追踪当操作数没有任何异常位设置的推测指令遇到异常情况时发生的原始推测异常。当在条件分支的采取路径中的非推测性指令使用来自其异常位置位的寄存器的操作数时，触发异常判定。异常条件和非推测性指令的存在产生异常解析（204）的异常信号（220）。推测异常解决（204）包括响应来自额外寄存器的输出信号和额外异常位，用于校正（204）导致异常并重新执行（208）指令的异常条件，这些指令取决于指令的结果，导致投机例外。本发明还处理这样的情况，其中推测性指令尝试使用其异常位如上所述设置的寄存器。

14. 发明公开

US20230153087A1 Method and system for converting a single-threaded software program into an application-specific supercomputer 审中-公开
公开(公告)号：US20230153087A1
公开(公告)日：2023-05-18
申请号：US18097420
申请日：2023-01-16
申请人： Kemal Ebcioglu , Emre Kultursay
发明人： Kemal Ebcioglu , Emre Kultursay
IPC分类号： G06F8/41 , G06F8/40 , G06F9/52 , G06F15/173 , G06F30/30 , G06F30/392
CPC分类号： G06F8/4452 , G06F8/40 , G06F9/52 , G06F15/17381 , G06F8/452 , G06F30/30 , G06F30/392 , G06F2115/10
摘要： The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

15. 发明授权

US11579854B2 Method and system for converting a single-threaded software program into an application-specific supercomputer 有权
公开(公告)号：US11579854B2
公开(公告)日：2023-02-14
申请号：US17411116
申请日：2021-08-25
申请人： Kemal Ebcioglu , Emre Kultursay
发明人： Kemal Ebcioglu , Emre Kultursay
IPC分类号： G06F8/41 , G06F8/40 , G06F9/52 , G06F15/173 , G06F30/30 , G06F30/392 , G06F115/10
摘要： The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

16. 发明授权

US10514939B2 Parallel hardware hypervisor for virtualizing application-specific supercomputers 有权
公开(公告)号：US10514939B2
公开(公告)日：2019-12-24
申请号：US16105741
申请日：2018-08-20
申请人： Kemal Ebcioglu , Atakan Dogan , Reha Oguz Altug
发明人： Kemal Ebcioglu , Atakan Dogan , Reha Oguz Altug
IPC分类号： G06F9/455 , G06F9/50 , G06F15/78
摘要： A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.

17. 发明申请

US20190114158A1 Method and system for converting a single-threaded software program into an application-specific supercomputer 审中-公开
公开(公告)号：US20190114158A1
公开(公告)日：2019-04-18
申请号：US16166164
申请日：2018-10-22
申请人： Kemal Ebcioglu , Emre Kultursay
发明人： Kemal Ebcioglu , Emre Kultursay
IPC分类号： G06F8/41 , G06F17/50 , G06F9/52 , G06F15/173 , G06F8/40
摘要： The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

18. 发明授权

US08825982B2 Storage unsharing 有权
标题翻译：存储取消共享
公开(公告)号：US08825982B2
公开(公告)日：2014-09-02
申请号：US13156881
申请日：2011-06-09
申请人： Emre Kultursay , Kemal Ebcioglu , Mahmut Taylan Kandemir
发明人： Emre Kultursay , Kemal Ebcioglu , Mahmut Taylan Kandemir
IPC分类号： G06F13/28 , G06F17/50 , G06F12/08
CPC分类号： G06F17/5045 , G06F12/0806 , G06F2217/68 , Y02D10/13
摘要： A method is described to partition the memory of application-specific hardware compiled from a software program. Applying the invention generates multiple small memories that need not be kept coherent and are defined over a specific region of the program. The invention creates application specific hardware which preserves the memory image and addressing model of the original software program. The memories are dynamically initialized and flushed at the entries and exits of the program region they are defined in.
摘要翻译：描述了一种方法来分配从软件程序编译的特定于应用程序的硬件的内存。应用本发明产生不需要保持一致的多个小存储器并且在程序的特定区域上定义。本发明创建应用专用硬件，其保留原始软件程序的存储器图像和寻址模型。这些存储器在它们定义的程序区域的条目和出口处被动态初始化和刷新。

19. 发明授权

US07516276B2 Runtime register allocator 失效
标题翻译：运行时寄存器分配器
公开(公告)号：US07516276B2
公开(公告)日：2009-04-07
申请号：US11929879
申请日：2007-10-30
申请人： Kartik Agaram , Marc A. Auslander , Kemal Ebcioglu
发明人： Kartik Agaram , Marc A. Auslander , Kemal Ebcioglu
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/3832 , G06F12/0862
摘要： Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.
摘要翻译：访问存储结构的方法和布置。包括用于提供存储访问指令的装置，用于响应于存储访问指令将地址输入存储结构数据高速缓存的布置，用于扩展具有预测寄存器号字段的存储访问指令的布置，预测寄存器号字段包含对应于与存储访问指令相关联的加载/存储操作数的推测位置的预测寄存器编号，用于通过扩展装置扩展的存储访问指令来推测访问存储结构的布置，以及用于恢复到布置如果加载/存储操作数不在投机位置，则输入地址。

20. 发明授权

US06349361B1 Methods and apparatus for reordering and renaming memory references in a multiprocessor computer system 失效
标题翻译：在多处理器计算机系统中重新排序和重命名内存引用的方法和装置
公开(公告)号：US06349361B1
公开(公告)日：2002-02-19
申请号：US09541271
申请日：2000-03-31
申请人： Erik Altman , Kemal Ebcioglu , Michael Gschwind , Sumedh Sathaye
发明人： Erik Altman , Kemal Ebcioglu , Michael Gschwind , Sumedh Sathaye
IPC分类号： G06F1200
CPC分类号： G06F9/3863 , G06F9/3834 , G06F9/3842 , G06F12/0815
摘要： There is provided a method for reordering and renaming memory references in a multiprocessor computer system having at least a first and a second processor. The first processor has a first private cache and a first buffer, and the second processor has a second private cache and a second buffer. The method includes the steps of, for each of a plurality of gated store requests received by the first processor to store a datum, exclusively acquiring a cache line that contains the datum by the first private cache, and storing the datum in the first buffer. Upon the first buffer receiving a load request from the first processor to load a particular datum, the particular datum is provided to the first processor from among the data stored in the first buffer based on an in-order sequence of load and store operations. Upon the first cache receiving a load request from the second cache for a given datum, an error condition is indicated and a current state of at least one of the processors is reset to an earlier state when the load request for the given datum corresponds to the data stored in the first buffer.
摘要翻译：提供了一种用于在具有至少第一和第二处理器的多处理器计算机系统中重新排序和重新命名存储器引用的方法。第一处理器具有第一私有缓存和第一缓冲器，并且第二处理器具有第二私有缓存和第二缓冲器。该方法包括以下步骤：针对由第一处理器接收的存储数据的多个门控存储请求中的每一个，独占地通过第一专用高速缓存器采集包含数据的高速缓存行，并将该数据存储在第一缓冲器中。在第一缓冲器接收到来自第一处理器的加载请求以加载特定数据时，基于加载和存储操作的按顺序将特定数据从存储在第一缓冲器中的数据提供给第一处理器。当第一缓存器从给定数据的第二高速缓存接收到加载请求时，指示错误状况，并且当给定数据的加载请求对应于该处理器的加载请求时，将至少一个处理器的当前状态重置为较早状态存储在第一缓冲区中的数据。

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