专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06307776B1 Multi-bit-per-cell flash EEPROM memory with refresh 失效
标题翻译：多单元快闪EEPROM存储器刷新
公开(公告)号：US06307776B1
公开(公告)日：2001-10-23
申请号：US09680797
申请日：2000-10-06
申请人： Hock C. So , Sau C. Wong
发明人： Hock C. So , Sau C. Wong
IPC分类号： G11C1604
CPC分类号： G06F11/1072 , B64C27/006 , G01N29/14 , G01N29/227 , G06F11/106 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/04 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/00 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2211/5634
摘要： A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.
摘要翻译：多单元单元非易失性存储器将存储器单元的适当阈值电压划分为对应于用于存储数据的允许状态的范围和对应于指示数据错误的禁止区域的范围。读取过程自动检查阈值电压是否处于禁止区。在替代实施例中，刷新过程包括将阈值电压重新编程为允许状态。在闪速存储器的情况下，刷新读取存储器的扇区，并将来自扇区的校正数据保存在缓冲器或另一扇区中。来自缓冲器或其他扇区的校正数据可以被写回到原始扇区中，或者校正的数据可以留在另一扇区中，原始扇区的地址映射到另一个扇区。非易失性存储器的刷新过程可以响应于检测到禁止区域中的阈值电压而进行，作为存储器的加电过程的一部分，或者周期性地在几天，几周或几个月的周期内。作为另一方面，允许的状态对应于灰度编码数字值，使得在阈值电压中相邻的允许状态对应于仅在单个位中不同的多位值。错误检测和校正码可用于识别数据错误，并生成用于刷新操作的校正数据。

12. 发明授权

US5949716A Look-ahead erase for sequential data storage 失效
标题翻译：先进的擦除用于顺序数据存储
公开(公告)号：US5949716A
公开(公告)日：1999-09-07
申请号：US839288
申请日：1997-04-16
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/04
CPC分类号： G11C16/16 , G11C16/08 , G11C16/10
摘要： Continuous recording in a flash memory uses a look-ahead erase process that includes simultaneously writing data to a first sector in a first array while preparing (erasing and/or partially programming) a second sector in a second array. The second sector is ready for writing when a last datum fills the first sector and is immediately available for writing while a third sector is prepared. The look-ahead erase keeps preparing sectors so that writing can continue without interruptions for erase processes. Embodiments of the invention include integrated circuit memories having two or more memory arrays, each having a plurality of independently erasable sectors. Each time a sector is filled the write process switches to a sector in another array.
摘要翻译：在闪速存储器中的连续记录使用先行擦除处理，其包括在准备（擦除和/或部分编程）第二阵列中的第二扇区的同时将数据写入第一阵列中的第一扇区。当最后一个数据填充第一个扇区并且在准备第三个扇区时，第二个扇区可以立即写入。先行擦除保持准备扇区，以便写入可以继续，而不会中断擦除过程。本发明的实施例包括具有两个或更多个存储器阵列的集成电路存储器，每个存储器阵列具有多个独立的可擦除扇区。每次扇区填充时，写入过程切换到另一个阵列中的扇区。

13. 发明授权

US5909449A Multibit-per-cell non-volatile memory with error detection and correction 失效
标题翻译：具有错误检测和校正功能的多单元单元非易失性存储器
公开(公告)号：US5909449A
公开(公告)日：1999-06-01
申请号：US924909
申请日：1997-09-08
申请人： Hock C. So , Sau C. Wong
发明人： Hock C. So , Sau C. Wong
IPC分类号： G11C16/02 , B64C27/00 , G01N29/14 , G01N29/22 , G06F11/10 , G11C11/56 , G11C16/06 , G11C29/42 , G11C29/50 , G06F11/00
CPC分类号： G06F11/1072 , B64C27/006 , G01N29/14 , G01N29/227 , G06F11/106 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3459 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C16/04 , G11C2211/5634 , G11C29/00
摘要： A multilevel non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state or in the case of a flash memory, reading a sector of the memory, saving data from the sector in a buffer, erasing the sector, and rewriting the data from the buffer back in the sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months.
摘要翻译：多级非易失性存储器将存储器单元的适当阈值电压划分为对应于用于存储数据的允许状态的范围和对应于指示数据错误的禁止区域的范围。读取过程自动检查阈值电压是否处于禁止区。在替代实施例中，刷新过程包括将阈值电压重新编程为允许状态或者在闪速存储器的情况下，读取存储器的扇区，在缓冲器中保存来自扇区的数据，擦除扇区，并将数据从缓冲区返回到扇区。非易失性存储器的刷新过程可以响应于检测到禁止区域中的阈值电压而进行，作为存储器的加电过程的一部分，或者周期性地在几天，几周或几个月的周期内。

14. 发明授权

US5801980A Testing of an analog memory using an on-chip digital input/output interface 失效
标题翻译：使用片上数字输入/输出接口测试模拟存储器
公开(公告)号：US5801980A
公开(公告)日：1998-09-01
申请号：US847236
申请日：1997-05-01
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G01R31/3167 , G11C7/16 , G11C8/04 , G11C11/56 , G11C27/00 , G11C29/20
CPC分类号： G11C8/04 , G01R31/3167 , G11C11/56 , G11C27/005 , G11C29/20 , G11C7/16 , G11C2211/5644
摘要： A non-volatile memory stores both analog and digital information in an array, and has digital and analog read and write circuits and dual I/O interfaces which allow input and output signals in digital or analog form. A user selects the input signal, output signal, and data storage formats. Each selection can be digital or analog format. On-chip analog-to-digital and digital-to-analog converters allow conversion of signals from one format into another. Analog signals can be read or written serially, and one embodiment includes an address counter and an internal oscillator for generating sequential addresses. An output amplifier for driving a speaker and an input amplifier for a microphone allow stored sounds to be directly recorded and reproduced.
摘要翻译：非易失性存储器将模拟和数字信息存储在阵列中，并具有数字和模拟读写电路和允许数字或模拟形式的输入和输出信号的双I / O接口。用户选择输入信号，输出信号和数据存储格式。每个选择可以是数字或模拟格式。片上模拟数字和数模转换器允许将信号从一种格式转换为另一种格式。可以串行地读取或写入模拟信号，并且一个实施例包括用于产生顺序地址的地址计数器和内部振荡器。用于驱动扬声器的输出放大器和用于麦克风的输入放大器允许存储的声音被直接记录和再现。

15. 发明授权

US5751635A Read circuits for analog memory cells 失效
标题翻译：读模拟存储单元的电路
公开(公告)号：US5751635A
公开(公告)日：1998-05-12
申请号：US585072
申请日：1996-01-11
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G11C16/02 , G11C11/56 , G11C16/06 , G11C16/34 , G11C27/00 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C27/005 , G11C2211/5621 , G11C7/16
摘要： Circuits and processes write and read analog signals in non-volatile memory cells such as EPROM and flash EPROM cells. One read circuit process determines a memory cell's threshold voltage by slowly ramps the control gate voltage of a memory cell being read and senses when the memory cell conducts. Another read circuit determines the threshold voltage of a memory cell using a source follower read process and a ramping circuit which slowly increases the source voltage. Still another read circuit includes a cascoding device connectable to a memory cell, bias circuit for biasing the memory cell in its linear region, and a load which carries a current that mirrors the current through the memory cell wherein the threshold voltage of the memory cell is determined from a voltage across the load. Read circuits disclosed can be used with analog memory cells, binary memory cells, multi-level digital memory cells, and other applications which require precise reading of threshold voltages.
摘要翻译：电路和过程在诸如EPROM和闪存EPROM单元的非易失性存储单元中写入和读取模拟信号。一个读取电路处理通过缓慢地斜升正在读取的存储单元的控制栅极电压来确定存储单元的阈值电压，并感测存储器单元何时导通。另一个读取电路使用源极跟随器读取处理和缓慢增加源极电压的斜坡电路来确定存储器单元的阈值电压。另一个读取电路包括可连接到存储器单元的级联装置，用于偏置其线性区域中的存储单元的偏置电路和承载反映通过存储单元的电流的电流的负载，其中存储单元的阈值电压为由负载上的电压确定。所公开的读出电路可以与需要精确读取阈值电压的模拟存储器单元，二进制存储器单元，多级数字存储单元以及其他应用一起使用。

16. 发明授权

US5748534A Feedback loop for reading threshold voltage 失效
标题翻译：用于读取阈值电压的反馈回路
公开(公告)号：US5748534A
公开(公告)日：1998-05-05
申请号：US622333
申请日：1996-03-26
申请人： Frank M. Dunlap , Hock C. So , Sau C. Wong
发明人： Frank M. Dunlap , Hock C. So , Sau C. Wong
IPC分类号： G11C11/56 , G11C16/28 , G11C16/34 , G11C27/00 , G11C11/34
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/28 , G11C27/005
摘要： To read the threshold voltage of a transistor such as a floating gate transistor in an analog or multi-level memory cell, the transistor is connected in a feedback loop which contains a differential amplifier having an output terminal and an input terminal respectively connected to the gate and a node (source or drain) of the transistor. A reference voltage is asserted to a second input terminal of the differential amplifier. A load provides a current which charges the node, and the differential amplifier adjusts the gate voltage of the memory cell to an equilibrium value where current through the transistor is equal to current through the reference cell. The equilibrium value of the gate voltage depends on and indicates the threshold voltage of the transistor. In one embodiment of the invention, the load is a current source which mirrors a current through a reference cell that is structurally identical to the transistor, and the drain of the reference cell provides the reference voltage to the amplifier.
摘要翻译：为了读取诸如模拟或多电平存储单元中的浮栅晶体管的晶体管的阈值电压，晶体管连接在反馈回路中，该反馈环包含具有分别连接到栅极的输出端和输入端的差分放大器和晶体管的一个节点（源极或漏极）。参考电压被确定到差分放大器的第二输入端。负载提供对节点充电的电流，并且差分放大器将存储器单元的栅极电压调整到平衡值，其中通过晶体管的电流等于通过参考单元的电流。栅极电压的平衡值取决于晶体管的阈值电压。在本发明的一个实施例中，负载是电流源，其反射通过结构上与晶体管相同的参考单元的电流，并且参考单元的漏极将参考电压提供给放大器。

17. 发明授权

US5745409A Non-volatile memory with analog and digital interface and storage 失效
标题翻译：具有模拟和数字接口和存储的非易失性存储器
公开(公告)号：US5745409A
公开(公告)日：1998-04-28
申请号：US535441
申请日：1995-09-28
申请人： Sau C. Wong , Hock C. So
发明人： Sau C. Wong , Hock C. So
IPC分类号： G01R31/3167 , G11C7/16 , G11C8/04 , G11C11/56 , G11C27/00 , G11C29/20 , G11C7/00
CPC分类号： G11C8/04 , G01R31/3167 , G11C11/56 , G11C27/005 , G11C29/20 , G11C7/16 , G11C2211/5644
摘要： A non-volatile memory stores both analog and digital information in an array, and has digital and analog read and write circuits and dual I/O interfaces which allow input and output signals in digital or analog form. A user selects the input signal, output signal, and data storage formats. Each selection can be digital or analog format. On-chip analog-to-digital and digital-to-analog converters allow conversion of signals from one format into another. Analog signals can be read or written serially, and one embodiment includes an address counter and an internal oscillator for generating sequential addresses. An output amplifier for driving a speaker and an input amplifier for a microphone allow stored sounds to be directly recorded and reproduced.
摘要翻译：非易失性存储器将模拟和数字信息存储在阵列中，并具有数字和模拟读写电路和允许数字或模拟形式的输入和输出信号的双I / O接口。用户选择输入信号，输出信号和数据存储格式。每个选择可以是数字或模拟格式。片上模拟数字和数模转换器允许将信号从一种格式转换为另一种格式。可以串行地读取或写入模拟信号，并且一个实施例包括用于产生顺序地址的地址计数器和内部振荡器。用于驱动扬声器的输出放大器和用于麦克风的输入放大器允许存储的声音被直接记录和再现。

18. 发明授权

US4713792A Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits 失效
标题翻译：可编程宏单元使用eprom或eeprom晶体管进行可编程逻辑电路中的架构控制
公开(公告)号：US4713792A
公开(公告)日：1987-12-15
申请号：US742089
申请日：1985-06-06
申请人： Robert F. Hartmann , Yiu-Fai Chan , Robert J. Frankovich , Jung-Hsing Ou , Hock C. So , Sau-Ching Wong
发明人： Robert F. Hartmann , Yiu-Fai Chan , Robert J. Frankovich , Jung-Hsing Ou , Hock C. So , Sau-Ching Wong
IPC分类号： G11C17/00 , G11C16/04 , H01L21/82 , H01L21/8247 , H01L29/788 , H01L29/792 , H03K17/693 , H03K19/173 , H03K19/177 , G06F1/00
CPC分类号： H03K19/1736 , H03K17/693 , H03K19/1737
摘要： A programmable macrocell 28 for use in an integrated circuit device including an electronic circuit 32 responsive to control signals and operative to perform particular operations selected by the control signals on input data signals and to develop commensurate output signals, and one or more architecture control circuits 30 each including a programmable EPROM device 34 which when programmed generates a logic signal of a first state and when unprogrammed generates a logic signal of a second state, a read and write control circuit 36 responsive to input program data signals and a corresponding address signal and operative to program the EPROM device 34 by applying a programming potential thereto, and a sensing circuit 38 for sensing the programmed or unprogrammed status of the EPROM device 34 and for developing a commensurate control signal for input to the electronic circuit 32.
摘要翻译：一种用于集成电路设备的可编程宏单元28，其包括响应于控制信号的电子电路32，并且可操作以执行由输入数据信号上的控制信号选择的特定操作并且开发相应的输出信号，以及一个或多个架构控制电路30 每个都包括一个可编程EPROM器件34，当被编程时产生第一状态的逻辑信号，并且当未编程产生第二状态的逻辑信号时，读和写控制电路36响应输入的程序数据信号和对应的地址信号，通过向其施加编程电位来对EPROM器件34进行编程;以及感测电路38，用于感测EPROM器件34的编程状态或未编程状态，并用于形成相应的控制信号以输入到电子电路32。

19. 发明授权

US07440327B1 Non-volatile storage with reduced power consumption during read operations 有权
标题翻译：非易失性存储器，在读取操作期间具有降低的功耗
公开(公告)号：US07440327B1
公开(公告)日：2008-10-21
申请号：US11740096
申请日：2007-04-25
申请人： Deepak Chandra Sekar , Nima Mokhlesi , Hock C. So
发明人： Deepak Chandra Sekar , Nima Mokhlesi , Hock C. So
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.
摘要翻译：一种非易失性存储装置，其中在读取操作期间通过在未选择的字线上提供减小的读取通过电压来降低功耗。检查在其上正在读取存储元件的所选字线之后的一个或多个未选字线的编程状态，以确定未选择的字线是否包含编程的存储元件。当识别出未编程的字线时，在该字线和在该字线之后的编程顺序中的其它字线提供减小的读通道电压。编程状态可以通过例如存储在字线中的标志来确定，或者通过在最低读取状态下读取字线来确定。被检查的未选择的字线可以在一组字线中预先确定，或者基于所选字线的位置自适应地确定。

20. 发明授权

US07106632B2 Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US07106632B2
公开(公告)日：2006-09-12
申请号：US10359476
申请日：2003-02-05
申请人： Carl W. Werner , Andreas M. Haeberli , Leon Sea Jiunn Wong , Cheng-Yuan Michael Wang , Hock C. So , Sau C. Wong
发明人： Carl W. Werner , Andreas M. Haeberli , Leon Sea Jiunn Wong , Cheng-Yuan Michael Wang , Hock C. So , Sau C. Wong
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式