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11. 发明授权

US5734188A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
公开(公告)号：US5734188A
公开(公告)日：1998-03-31
申请号：US674185
申请日：1996-07-01
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L27/105 , H01L29/76 , H01L29/94 , H01L31/062 , H01L3/119
CPC分类号： H01L27/105
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

12. 发明授权

US5202275A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5202275A
公开(公告)日：1993-04-13
申请号：US496330
申请日：1990-03-20
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在所述衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

13. 发明授权

US07526948B2 Device and method for detecting foreign material on the surface of plasma processing apparatus 失效
标题翻译：用于检测等离子体处理装置表面的异物的装置和方法
公开(公告)号：US07526948B2
公开(公告)日：2009-05-05
申请号：US11214963
申请日：2005-08-31
申请人： Hideyuki Yamamoto , Hiromichi Enami , Muneo Furuse
发明人： Hideyuki Yamamoto , Hiromichi Enami , Muneo Furuse
IPC分类号： G01N1/08 , G01M19/00 , H01L21/66
CPC分类号： G01N1/24 , G01N2015/1062 , H01L21/02057
摘要： A detection technique for detecting foreign material on the surface of a plasma processing apparatus, capable of accurately sucking/extracting and measuring foreign material contained in the measurement object surface is provided. The detection device comprises a gauge head or probe having a gas blow out opening for intermittently blowing a gas of a predetermined pressure to a measurement object surface and a gas suction opening for sucking foreign material discharged by the gas blown out from the gas blow out opening a particle counter having a suction pump for continuously sucking in a predetermined amount of gas from the gas suction opening for counting the number of foreign material particles contained in the gas sucked by the suction pump and a pressure adjustment unit for intermittently supplying gas of a predetermined pressure to the gas blowing out opening.
摘要翻译：提供一种用于检测等离子体处理装置表面上异物的检测技术，其能够精确地吸取/提取和测量包含在测量对象表面中的异物。检测装置包括具有用于间歇地向测量对象表面吹送预定压力的气体的气体吹出口的测量头或探针，以及用于吸入从气体吹出口吹出的气体排出的异物的吸气口具有吸入泵的颗粒计数器，用于连续吸入来自吸入口的预定量的气体，用于计数由吸入泵抽吸的气体中包含的异物颗粒的数量;以及压力调节单元，用于间歇地供给预定的对气体吹出口的压力。

14. 发明申请

US20070032088A1 Device and method for detecting foreign material on the surface of plasma processing apparatus 失效
标题翻译：用于检测等离子体处理装置表面的异物的装置和方法
公开(公告)号：US20070032088A1
公开(公告)日：2007-02-08
申请号：US11214963
申请日：2005-08-31
申请人： Hideyuki Yamamoto , Hiromichi Enami , Muneo Furuse
发明人： Hideyuki Yamamoto , Hiromichi Enami , Muneo Furuse
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： G01N1/24 , G01N2015/1062 , H01L21/02057
摘要： A detection technique for detecting foreign material on the surface of a plasma processing apparatus, capable of accurately sucking/extracting and measuring foreign material contained in the measurement object surface is provided. The detection device comprises a gauge head or probe having a gas blow out opening for intermittently blowing a gas of a predetermined pressure to a measurement object surface and a gas suction opening for sucking foreign material discharged by the gas blown out from the gas blow out opening a particle counter having a suction pump for continuously sucking in a predetermined amount of gas from the gas suction opening for counting the number of foreign material particles contained in the gas sucked by the suction pump and a pressure adjustment unit for intermittently supplying gas of a predetermined pressure to the gas blowing out opening.
摘要翻译：提供一种用于检测等离子体处理装置表面上异物的检测技术，其能够精确地吸取/提取和测量包含在测量对象表面中的异物。检测装置包括具有用于间歇地向测量对象表面吹送预定压力的气体的气体吹出口的测量头或探针，以及用于吸入从气体吹出口吹出的气体排出的异物的吸气口具有吸入泵的颗粒计数器，用于连续吸入来自吸入口的预定量的气体，用于计数由吸入泵抽吸的气体中包含的异物颗粒的数量;以及压力调节单元，用于间歇地供给预定的对气体吹出口的压力。

15. 发明授权

US06923885B2 Plasma processing system and apparatus and a sample processing method 有权
标题翻译：等离子体处理系统和设备及样品处理方法
公开(公告)号：US06923885B2
公开(公告)日：2005-08-02
申请号：US10732286
申请日：2003-12-11
申请人： Toshio Masuda , Tatehito Usui , Mitsuru Suehiro , Hiroshi Kanekiyo , Hideyuki Yamamoto , Kazue Takahashi , Hiromichi Enami
发明人： Toshio Masuda , Tatehito Usui , Mitsuru Suehiro , Hiroshi Kanekiyo , Hideyuki Yamamoto , Kazue Takahashi , Hiromichi Enami
IPC分类号： H01L21/3065 , H01J37/32 , H01L21/00 , C23C16/00
CPC分类号： H01L21/67069 , G01N21/68 , H01J37/32082 , H01J37/32935 , H01J37/32972
摘要： A plasma processing apparatus having a sample bench located in a vacuum chamber, a structure disposed at a position opposed to a sample placed on the sample bench and facing a plasma generated in the vacuum chamber, and at least one through-hole disposed in the structure through which a gas flows into the vacuum chamber. An optical transmitter is mounted on a back of the at least one through-hole through which light from the sample passes, which light is detected by way of the optical transmitter.
摘要翻译：一种等离子体处理装置，其具有位于真空室中的样品台，设置在与放置在样品台上的样品相对的位置并且面对在真空室中产生的等离子体的结构，以及设置在该结构中的至少一个通孔气体通过该气体流入真空室。光传输器安装在所述至少一个通孔的背面上，来自所述样品的光通过所述至少一个通孔穿过，所述光通过所述光发射器检测。

16. 发明授权

US06754552B2 Control apparatus for plasma utilizing equipment 失效
标题翻译：等离子体利用设备的控制装置
公开(公告)号：US06754552B2
公开(公告)日：2004-06-22
申请号：US09797579
申请日：2001-03-05
申请人： Masaharu Nishiumi , Hiromichi Enami
发明人： Masaharu Nishiumi , Hiromichi Enami
IPC分类号： G06F1900
CPC分类号： H01L21/67253 , H01J37/32935
摘要： A plurality of measuring devices to obtain numerical information necessary for control in process control of plasma utilizing equipment are connected to a first communication link, a plurality controllers to conduct numerical operations according to the numerical information are connected to a second communication link, and a plurality of control devices to receive control numerical information generated by the controllers to conduct necessary control.
摘要翻译：用于获得等离子体利用设备的过程控制中控制所必需的数值信息的多个测量装置连接到第一通信链路，根据数字信息进行数字操作的多个控制器被连接到第二通信链路，并且多个的控制装置接收由控制器产生的控制数字信息以进行必要的控制。

17. 发明授权

US06169324A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06169324A
公开(公告)日：2001-01-02
申请号：US09413754
申请日：1999-10-06
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2144
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

18. 发明授权

US5780882A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
公开(公告)号：US5780882A
公开(公告)日：1998-07-14
申请号：US456788
申请日：1995-06-01
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

19. 发明授权

US5543336A Removing damage caused by plasma etching and high energy implantation using hydrogen 失效
标题翻译：消除等离子体蚀刻造成的损伤和使用氢的高能量注入
公开(公告)号：US5543336A
公开(公告)日：1996-08-06
申请号：US348108
申请日：1994-11-25
申请人： Hiromichi Enami , Kiyomi Katsuyama , Masanori Katsuyama
发明人： Hiromichi Enami , Kiyomi Katsuyama , Masanori Katsuyama
IPC分类号： H01L21/302 , H01L21/00 , H01L21/265 , H01L21/30 , H01L21/3065 , H01L21/324 , H01L21/266
CPC分类号： H01L21/67167 , H01L21/3003 , H01L21/67069 , H01L21/67213
摘要： A chamber 103 for introducing hydrogen without causing serious damage to a semiconductor wafer and a chamber 104 for eliminating the hydrogen introduced into the semiconductor wafer at relatively low temperature are installed at the succeeding stage of a plasma etching unit for effectively correcting the damage caused by plasma etching and ion implantation to a semiconductor substrate or an ion implanting unit. In order to introduce hydrogen into the semiconductor wafer without serious damage, a mixture of hydrocarbon gas and oxygen gas for accelerating the decomposition of the hydrocarbon gas is used for forming hydrogen radicals in a plasma and the hydrogen radicals are supplied to the semiconductor wafer at room temperature by a downstream system. The semiconductor wafer is heat-treated in an atmosphere of a vacuum or inactive gas in a temperature region of 200.degree.-500.degree. C. to eliminate the hydrogen introduced into the semiconductor wafer.
摘要翻译：在等离子体蚀刻单元的后续阶段安装有用于引入氢而不对半导体晶片造成严重损坏的室103和用于消除在较低温度下引入到半导体晶片中的氢的室104，用于有效地校正由等离子体蚀刻和离子注入到半导体衬底或离子注入单元。为了在没有严重损坏的情况下将氢气引入半导体晶片中，使用用于加速烃气体分解的烃气体和氧气的混合物在等离子体中形成氢自由基，并且在室内将氢自由基供应到半导体晶片温度由下游系统。半导体晶片在真空或惰性气体气氛中在200-500℃的温度范围内进行热处理，以消除引入到半导体晶片中的氢。

20. 发明授权

US5264712A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5264712A
公开(公告)日：1993-11-23
申请号：US881314
申请日：1992-05-07
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L21/308 , H01L29/66
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

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