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11. 发明授权

US07767562B2 Method of implanting using a shadow effect 有权
标题翻译：使用阴影效果进行植入的方法
公开(公告)号：US07767562B2
公开(公告)日：2010-08-03
申请号：US11235330
申请日：2005-09-26
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L21/425
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
摘要翻译：半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

12. 发明申请

US20090160020A1 Moisture Barrier Capacitors in Semiconductor Components 有权
标题翻译：半导体元件中的阻水电容器
公开(公告)号：US20090160020A1
公开(公告)日：2009-06-25
申请号：US11962395
申请日：2007-12-21
申请人： Hans-Joachim Barth , Helmut Horst Tews
发明人： Hans-Joachim Barth , Helmut Horst Tews
IPC分类号： H01L29/92 , H01L21/02 , H01L21/66
CPC分类号： H01L28/75 , G06F17/5068 , H01L21/76897 , H01L22/14 , H01L23/5223 , H01L23/5226 , H01L23/562 , H01L23/585 , H01L27/0611 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
摘要翻译：公开了在半导体部件上形成防潮电容器的结构和方法。电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

13. 发明授权

US06740555B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06740555B1
公开(公告)日：2004-05-25
申请号：US09408248
申请日：1999-09-29
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅，厚度大于<100>平面上的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

14. 发明授权

US06670235B1 Process flow for two-step collar in DRAM preparation 有权
标题翻译： DRAM制程中两步领的工艺流程
公开(公告)号：US06670235B1
公开(公告)日：2003-12-30
申请号：US09939554
申请日：2001-08-28
申请人： Helmut Horst Tews , Stephan Kudelka , Oliver Genz
发明人： Helmut Horst Tews , Stephan Kudelka , Oliver Genz
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/1087
摘要： In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing comprising: a) forming a pad nitride on the surface of the substrate and reactive ion etching (RIE) a trench vertically to a first depth; b) depositing a nitride layer in the trench; c) filling the trench with a poly silicon fill; d) recess etching the fill to the collar depth; e) oxidizing to transform the exposed nitride layer into a nitrided oxide collar or depositing an oxide on the layer of nitride; f) reactive ion etching to open the bottom oxide; g) stripping the poly fill trench, and performing a nitride etch selective to oxide; h) expanding the trench horizontally by etching lower trench sidewalls and bottom while masking the upper sidewalls; i) forming a buried plate at the bottom of the trench sidewalls; j) forming the node dielectric in the deep trench to grow a collar oxide that consists of a nitrided oxide and a layer of node nitride; k) filling the trench with a poly fill; l) recess etching the poly fill approximately to the collar bottom; m) depositing a collar oxide; n) reactive ion etching to open the bottom; o) filling the trench with a poly fill; and p) chemically mechanically polishing the semiconductor substrate.
摘要翻译：在半导体衬底中形成DRAM单元的方法中，在沟槽处理期间保持基本上完整的沟槽开口的改进包括：a）在衬底的表面上形成衬垫氮化物，并且反应离子蚀刻（RIE）垂直于第一深度; b）在沟槽中沉积氮化物层; c）用多晶硅填充物填充沟槽; d）将填充物凹陷蚀刻到套环深度; e）氧化以将暴露的氮化物层转变成氮化的氧化物环或在氮化物层上沉积氧化物; f）反应离子蚀刻以打开底部氧化物; g）剥离多晶填充沟槽，并对氧化物进行选择性的氮化物蚀刻; h）通过在掩蔽上侧壁的同时蚀刻下沟槽侧壁和底部来水平地扩展沟槽; i）在沟槽侧壁的底部形成掩埋板; j）在深沟槽中形成节点电介质以生长由氮化氧化物和节点氮化物层组成的环状氧化物; k）用多孔填充物填充沟槽; l）凹槽将多孔填充物蚀刻到接近底部; m）沉积环氧化物; n）反应离子蚀刻打开底部; o）用多孔填充填充沟槽; 和p）化学机械抛光半导体衬底。

15. 发明授权

US06486024B1 Integrated circuit trench device with a dielectric collar stack, and method of forming thereof 失效
标题翻译：具有介质套管叠层的集成电路沟槽器件及其形成方法
公开(公告)号：US06486024B1
公开(公告)日：2002-11-26
申请号：US09577102
申请日：2000-05-24
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.
摘要翻译：一种使用至少两个绝缘层以形成沟槽器件的隔离套环的方法，以及由其形成的器件。第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。优选地，TEOS工艺和LOCOS工艺都用于形成第一层。第二层优选是形成在氧化物层上的氮化硅层（114）。多层用作沟槽的隔离环叠层。第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

16. 发明授权

US06372567B1 Control of oxide thickness in vertical transistor structures 有权
标题翻译：垂直晶体管结构中氧化物厚度的控制
公开(公告)号：US06372567B1
公开(公告)日：2002-04-16
申请号：US09553708
申请日：2000-04-20
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
IPC分类号： H01L218238
CPC分类号： H01L21/28211 , H01L21/2236 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10873 , H01L29/045
摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.
摘要翻译：在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击足以产生氧化物侧壁的非晶层的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和重结晶。

17. 发明申请

US20110278680A1 Strained Semiconductor Device and Method of Making the Same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20110278680A1
公开(公告)日：2011-11-17
申请号：US13193692
申请日：2011-07-29
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

18. 发明申请

US20100330771A1 Moisture Barrier Capacitors in Semiconductor Components 审中-公开
标题翻译：半导体元件中的阻水电容器
公开(公告)号：US20100330771A1
公开(公告)日：2010-12-30
申请号：US12876866
申请日：2010-09-07
申请人： Hans-Joachim Barth , Helmut Horst Tews
发明人： Hans-Joachim Barth , Helmut Horst Tews
IPC分类号： H01L21/02
CPC分类号： H01L28/75 , G06F17/5068 , H01L21/76897 , H01L22/14 , H01L23/5223 , H01L23/5226 , H01L23/562 , H01L23/585 , H01L27/0611 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
摘要翻译：公开了在半导体部件上形成防潮电容器的结构和方法。电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

19. 发明授权

US07157328B2 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US07157328B2
公开(公告)日：2007-01-02
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
发明人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
IPC分类号： H01L21/8242
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

20. 发明授权

US06967147B1 Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor 失效
标题翻译：使用阴影效应的氮注入来控制DRAM半导体中的栅极氧化物厚度
公开(公告)号：US06967147B1
公开(公告)日：2005-11-22
申请号：US09714356
申请日：2000-11-16
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L20060101 , H01L21/265 , H01L21/28 , H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/06
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.
摘要翻译：用于通过使用氮注入并入不同厚度的栅极氧化物来形成用于DRAMS的双栅极氧化物的工艺。使用倾斜的氮气注入或氮化物间隔物来产生“阴影效应”或区域，这限制了接近有效区域边缘的氮剂量。氮剂量的减少导致在与浅沟槽相邻的有源区（AA）处的栅极氧化物厚度增加，增加了寄生角装置的阈值并且减小了副Vt（阈值电压）和结漏电。

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