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1. 发明授权

US06670235B1 Process flow for two-step collar in DRAM preparation 有权
标题翻译： DRAM制程中两步领的工艺流程
公开(公告)号：US06670235B1
公开(公告)日：2003-12-30
申请号：US09939554
申请日：2001-08-28
申请人： Helmut Horst Tews , Stephan Kudelka , Oliver Genz
发明人： Helmut Horst Tews , Stephan Kudelka , Oliver Genz
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/1087
摘要： In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing comprising: a) forming a pad nitride on the surface of the substrate and reactive ion etching (RIE) a trench vertically to a first depth; b) depositing a nitride layer in the trench; c) filling the trench with a poly silicon fill; d) recess etching the fill to the collar depth; e) oxidizing to transform the exposed nitride layer into a nitrided oxide collar or depositing an oxide on the layer of nitride; f) reactive ion etching to open the bottom oxide; g) stripping the poly fill trench, and performing a nitride etch selective to oxide; h) expanding the trench horizontally by etching lower trench sidewalls and bottom while masking the upper sidewalls; i) forming a buried plate at the bottom of the trench sidewalls; j) forming the node dielectric in the deep trench to grow a collar oxide that consists of a nitrided oxide and a layer of node nitride; k) filling the trench with a poly fill; l) recess etching the poly fill approximately to the collar bottom; m) depositing a collar oxide; n) reactive ion etching to open the bottom; o) filling the trench with a poly fill; and p) chemically mechanically polishing the semiconductor substrate.
摘要翻译：在半导体衬底中形成DRAM单元的方法中，在沟槽处理期间保持基本上完整的沟槽开口的改进包括：a）在衬底的表面上形成衬垫氮化物，并且反应离子蚀刻（RIE）垂直于第一深度; b）在沟槽中沉积氮化物层; c）用多晶硅填充物填充沟槽; d）将填充物凹陷蚀刻到套环深度; e）氧化以将暴露的氮化物层转变成氮化的氧化物环或在氮化物层上沉积氧化物; f）反应离子蚀刻以打开底部氧化物; g）剥离多晶填充沟槽，并对氧化物进行选择性的氮化物蚀刻; h）通过在掩蔽上侧壁的同时蚀刻下沟槽侧壁和底部来水平地扩展沟槽; i）在沟槽侧壁的底部形成掩埋板; j）在深沟槽中形成节点电介质以生长由氮化氧化物和节点氮化物层组成的环状氧化物; k）用多孔填充物填充沟槽; l）凹槽将多孔填充物蚀刻到接近底部; m）沉积环氧化物; n）反应离子蚀刻打开底部; o）用多孔填充填充沟槽; 和p）化学机械抛光半导体衬底。

2. 发明授权

US07157328B2 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US07157328B2
公开(公告)日：2007-01-02
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
发明人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
IPC分类号： H01L21/8242
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

3. 发明授权

US06677197B2 High aspect ratio PBL SiN barrier formation 有权
标题翻译：高纵横比PBL SiN阻挡层形成
公开(公告)号：US06677197B2
公开(公告)日：2004-01-13
申请号：US10032040
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews
发明人： Stephan Kudelka , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.
摘要翻译：在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a）在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物进行多化学机械抛光。

4. 发明授权

US06740555B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06740555B1
公开(公告)日：2004-05-25
申请号：US09408248
申请日：1999-09-29
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅，厚度大于<100>平面上的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

5. 发明授权

US06486024B1 Integrated circuit trench device with a dielectric collar stack, and method of forming thereof 失效
标题翻译：具有介质套管叠层的集成电路沟槽器件及其形成方法
公开(公告)号：US06486024B1
公开(公告)日：2002-11-26
申请号：US09577102
申请日：2000-05-24
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.
摘要翻译：一种使用至少两个绝缘层以形成沟槽器件的隔离套环的方法，以及由其形成的器件。第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。优选地，TEOS工艺和LOCOS工艺都用于形成第一层。第二层优选是形成在氧化物层上的氮化硅层（114）。多层用作沟槽的隔离环叠层。第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

6. 发明授权

US06555430B1 Process flow for capacitance enhancement in a DRAM trench 失效
标题翻译： DRAM沟槽中电容增强的工艺流程
公开(公告)号：US06555430B1
公开(公告)日：2003-04-29
申请号：US09723420
申请日：2000-11-28
申请人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
发明人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , Y10S438/964
摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.
摘要翻译：提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

7. 发明授权

US06426253B1 Method of forming a vertically oriented device in an integrated circuit 有权
标题翻译：在集成电路中形成垂直取向器件的方法
公开(公告)号：US06426253B1
公开(公告)日：2002-07-30
申请号：US09576465
申请日：2000-05-23
申请人： Helmut Horst Tews , Alexander Michaelis , Brian S. Lee , Uwe Schroeder , Stephan Kudelka
发明人： Helmut Horst Tews , Alexander Michaelis , Brian S. Lee , Uwe Schroeder , Stephan Kudelka
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/76237 , H01L21/823487 , H01L27/10841 , H01L27/10867
摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.
摘要翻译：使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分沟槽暴露进一步加工。或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

8. 发明授权

US06335247B1 Integrated circuit vertical trench device and method of forming thereof 有权
标题翻译：集成电路垂直沟槽器件及其形成方法
公开(公告)号：US06335247B1
公开(公告)日：2002-01-01
申请号：US09597389
申请日：2000-06-19
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Brian S. Lee
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Brian S. Lee
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10876
摘要： A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.
摘要翻译：一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底侧壁（324）与单晶面。单侧垂直沟槽晶体管可以形成在平坦侧壁上。形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

9. 发明授权

US06613642B2 Method for surface roughness enhancement in semiconductor capacitor manufacturing 失效
标题翻译：半导体电容器制造中表面粗糙度增强的方法
公开(公告)号：US06613642B2
公开(公告)日：2003-09-02
申请号：US10016075
申请日：2001-12-13
申请人： Stephen Rahn , Irene McStay , Helmut Horst Tews , Uwe Schroeder , Stephan Kudelka , Rajarao Jammy
发明人： Stephen Rahn , Irene McStay , Helmut Horst Tews , Uwe Schroeder , Stephan Kudelka , Rajarao Jammy
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L28/84 , H01L28/90
摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.
摘要翻译：公开了一种用于增加半导体器件中原始表面的表面积的方法。在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

10. 发明授权

US06559002B1 Rough oxide hard mask for DT surface area enhancement for DT DRAM 失效
标题翻译：用于DT DRAM的DT表面积增强的粗糙氧化物硬掩模
公开(公告)号：US06559002B1
公开(公告)日：2003-05-06
申请号：US10032041
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews , Stephen Rahn , Irene McStay , Uwe Schroeder
发明人： Stephan Kudelka , Helmut Horst Tews , Stephen Rahn , Irene McStay , Uwe Schroeder
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L28/84 , Y10S438/964
摘要： In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.
摘要翻译：在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f）使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。

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